Lines Matching refs:value
94 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
99 * @value: 32bit eSDHC register value on spec_reg address
106 * Return a fixed up register value
109 int spec_reg, u32 value)
119 * And for many FSL eSDHC controller, the reset value of field
123 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
125 ret = value | SDHCI_CAN_DO_ADMA2;
138 ret = value & 0x000fffff;
139 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
140 ret |= (value << 1) & SDHCI_CMD_LVL;
160 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
165 ret = value;
170 int spec_reg, u32 value)
181 ret = value & 0xffff;
183 ret = (value >> shift) & 0xffff;
194 int spec_reg, u32 value)
200 ret = (value >> shift) & 0xff;
208 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
217 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
222 * @value: 8/16/32bit SD spec register value that would be written
223 * @old_value: 32bit eSDHC register value on spec_reg address
230 * Return a fixed up register value
233 int spec_reg, u32 value, u32 old_value)
243 ret = value | SDHCI_INT_BLK_GAP;
245 ret = value;
251 int spec_reg, u16 value, u32 old_value)
261 * command write that is down below. Return old value.
263 pltfm_host->xfer_mode_shadow = value;
266 ret = (value << 16) | pltfm_host->xfer_mode_shadow;
271 ret |= (value << shift);
285 int spec_reg, u8 value, u32 old_value)
311 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
313 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
322 ret = (old_value & (~(0xff << shift))) | (value << shift);
329 u32 value;
332 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
334 value = ioread32be(host->ioaddr + reg);
336 ret = esdhc_readl_fixup(host, reg, value);
344 u32 value;
347 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
349 value = ioread32(host->ioaddr + reg);
351 ret = esdhc_readl_fixup(host, reg, value);
359 u32 value;
362 value = ioread32be(host->ioaddr + base);
363 ret = esdhc_readw_fixup(host, reg, value);
370 u32 value;
373 value = ioread32(host->ioaddr + base);
374 ret = esdhc_readw_fixup(host, reg, value);
381 u32 value;
384 value = ioread32be(host->ioaddr + base);
385 ret = esdhc_readb_fixup(host, reg, value);
392 u32 value;
395 value = ioread32(host->ioaddr + base);
396 ret = esdhc_readb_fixup(host, reg, value);
402 u32 value;
404 value = esdhc_writel_fixup(host, reg, val, 0);
405 iowrite32be(value, host->ioaddr + reg);
410 u32 value;
412 value = esdhc_writel_fixup(host, reg, val, 0);
413 iowrite32(value, host->ioaddr + reg);
421 u32 value;
424 value = ioread32be(host->ioaddr + base);
425 ret = esdhc_writew_fixup(host, reg, val, value);
433 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
447 u32 value;
450 value = ioread32(host->ioaddr + base);
451 ret = esdhc_writew_fixup(host, reg, val, value);
459 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
471 u32 value;
474 value = ioread32be(host->ioaddr + base);
475 ret = esdhc_writeb_fixup(host, reg, val, value);
482 u32 value;
485 value = ioread32(host->ioaddr + base);
486 ret = esdhc_writeb_fixup(host, reg, val, value);
526 u32 value;
536 value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
539 value |= ESDHC_DMA_SNOOP;
541 value &= ~ESDHC_DMA_SNOOP;
543 sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
661 /* Fix clock value. */
1066 /* For tuning mode, the sd clock divisor value
1076 * The eSDHC controller takes the data timeout value into account
1081 * Just set the timeout to the maximum value because the core will
1380 * esdhc->peripheral_clock would be assigned with a value
1382 * For some platforms, the clock value got by common clk
1400 * initialize it as 1 or 0 once, to override the different value