Lines Matching refs:val
400 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
404 value = esdhc_writel_fixup(host, reg, val, 0);
408 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
412 value = esdhc_writel_fixup(host, reg, val, 0);
416 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
425 ret = esdhc_writew_fixup(host, reg, val, value);
442 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
451 ret = esdhc_writew_fixup(host, reg, val, value);
468 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
475 ret = esdhc_writeb_fixup(host, reg, val, value);
479 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
486 ret = esdhc_writeb_fixup(host, reg, val, value);
576 u32 val, clk_en;
588 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
591 val |= clk_en;
593 val &= ~clk_en;
595 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
619 u32 val;
621 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
622 val |= ESDHC_FLUSH_ASYNC_FIFO;
623 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
800 u32 val, bus_width = 0;
817 val = sdhci_readl(host, ESDHC_PROCTL);
818 bus_width = val & ESDHC_CTRL_BUSWIDTH_MASK;
829 val = sdhci_readl(host, ESDHC_PROCTL);
830 val &= ~ESDHC_CTRL_BUSWIDTH_MASK;
831 val |= bus_width;
832 sdhci_writel(host, val, ESDHC_PROCTL);
844 val = sdhci_readl(host, ESDHC_TBCTL);
845 val &= ~ESDHC_TB_EN;
846 sdhci_writel(host, val, ESDHC_TBCTL);
853 val = sdhci_readl(host, ESDHC_DLLCFG1);
854 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
855 sdhci_writel(host, val, ESDHC_DLLCFG1);
885 u32 val;
894 val = sdhci_readl(host, ESDHC_PROCTL);
898 val &= ~ESDHC_VOLT_SEL;
899 sdhci_writel(host, val, ESDHC_PROCTL);
912 val |= ESDHC_VOLT_SEL;
913 sdhci_writel(host, val, ESDHC_PROCTL);
922 val |= ESDHC_VOLT_SEL;
923 sdhci_writel(host, val, ESDHC_PROCTL);
951 u32 val;
956 val = sdhci_readl(host, ESDHC_TBCTL);
958 val |= ESDHC_TB_EN;
960 val &= ~ESDHC_TB_EN;
961 sdhci_writel(host, val, ESDHC_TBCTL);
969 u32 val;
972 val = sdhci_readl(host, ESDHC_TBCTL);
973 val &= ~(0xf << 8);
974 val |= 8 << 8;
975 sdhci_writel(host, val, ESDHC_TBCTL);
980 val = sdhci_readl(host, ESDHC_TBCTL);
981 sdhci_writel(host, val, ESDHC_TBCTL);
986 val = sdhci_readl(host, ESDHC_TBSTAT);
987 val = sdhci_readl(host, ESDHC_TBSTAT);
989 *window_end = val & 0xff;
990 *window_start = (val >> 8) & 0xff;
1034 u32 val;
1038 val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) &
1040 val |= window_end & ESDHC_WNDW_END_PTR_MASK;
1041 sdhci_writel(host, val, ESDHC_TBPTR);
1044 val = sdhci_readl(host, ESDHC_TBCTL);
1045 val &= ~ESDHC_TB_MODE_MASK;
1046 val |= ESDHC_TB_MODE_SW;
1047 sdhci_writel(host, val, ESDHC_TBCTL);
1064 u32 val;
1094 val = sdhci_readl(host, ESDHC_TBCTL);
1095 val &= ~ESDHC_TB_MODE_MASK;
1096 val |= ESDHC_TB_MODE_3;
1097 sdhci_writel(host, val, ESDHC_TBCTL);
1159 val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1160 val |= ESDHC_FLW_CTL_BG;
1161 sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
1170 u32 val;
1177 val = sdhci_readl(host, ESDHC_TBCTL);
1178 if (val & ESDHC_HS400_MODE) {
1179 val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1180 val &= ~ESDHC_FLW_CTL_BG;
1181 sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
1183 val = sdhci_readl(host, ESDHC_SDCLKCTL);
1184 val &= ~ESDHC_CMD_CLK_CTL;
1185 sdhci_writel(host, val, ESDHC_SDCLKCTL);
1188 val = sdhci_readl(host, ESDHC_TBCTL);
1189 val &= ~ESDHC_HS400_MODE;
1190 sdhci_writel(host, val, ESDHC_TBCTL);
1193 val = sdhci_readl(host, ESDHC_DLLCFG0);
1194 val &= ~(ESDHC_DLL_ENABLE | ESDHC_DLL_FREQ_SEL);
1195 sdhci_writel(host, val, ESDHC_DLLCFG0);
1197 val = sdhci_readl(host, ESDHC_TBCTL);
1198 val &= ~ESDHC_HS400_WNDW_ADJUST;
1199 sdhci_writel(host, val, ESDHC_TBCTL);
1342 u32 val;
1397 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
1404 val |= ESDHC_PERIPHERAL_CLK_SEL;
1406 val &= ~ESDHC_PERIPHERAL_CLK_SEL;
1407 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);