Lines Matching defs:max_clk
36 const unsigned int max_clk[MMC_TIMING_NUM];
41 .max_clk[MMC_TIMING_MMC_HS] = 46500000,
42 .max_clk[MMC_TIMING_SD_HS] = 46500000,
47 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
48 .max_clk[MMC_TIMING_MMC_HS200] = 167000000,
53 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
54 .max_clk[MMC_TIMING_MMC_HS200] = 125000000,
59 .max_clk[MMC_TIMING_LEGACY] = 20000000,
60 .max_clk[MMC_TIMING_MMC_HS] = 42000000,
61 .max_clk[MMC_TIMING_SD_HS] = 40000000,
666 clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
672 while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256)
675 while (host->max_clk / pre_div / div > clock_fixup && div < 16)
701 host->mmc->actual_clock = host->max_clk / esdhc->div_ratio;
1144 clk = host->max_clk / (esdhc->div_ratio + 1);