Lines Matching defs:host
24 #include <linux/mmc/host.h>
97 * @host: pointer to sdhci_host
108 static u32 esdhc_readl_fixup(struct sdhci_host *host,
111 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
155 * DTS properties of mmc host are used to enable each speed mode
169 static u16 esdhc_readw_fixup(struct sdhci_host *host,
172 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
193 static u8 esdhc_readb_fixup(struct sdhci_host *host,
220 * @host: pointer to sdhci_host
232 static u32 esdhc_writel_fixup(struct sdhci_host *host,
250 static u32 esdhc_writew_fixup(struct sdhci_host *host,
253 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
284 static u32 esdhc_writeb_fixup(struct sdhci_host *host,
304 * If host control register is not standard, exit
307 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
326 static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
332 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
334 value = ioread32be(host->ioaddr + reg);
336 ret = esdhc_readl_fixup(host, reg, value);
341 static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
347 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
349 value = ioread32(host->ioaddr + reg);
351 ret = esdhc_readl_fixup(host, reg, value);
356 static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
362 value = ioread32be(host->ioaddr + base);
363 ret = esdhc_readw_fixup(host, reg, value);
367 static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
373 value = ioread32(host->ioaddr + base);
374 ret = esdhc_readw_fixup(host, reg, value);
378 static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
384 value = ioread32be(host->ioaddr + base);
385 ret = esdhc_readb_fixup(host, reg, value);
389 static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
395 value = ioread32(host->ioaddr + base);
396 ret = esdhc_readb_fixup(host, reg, value);
400 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
404 value = esdhc_writel_fixup(host, reg, val, 0);
405 iowrite32be(value, host->ioaddr + reg);
408 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
412 value = esdhc_writel_fixup(host, reg, val, 0);
413 iowrite32(value, host->ioaddr + reg);
416 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
418 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
424 value = ioread32be(host->ioaddr + base);
425 ret = esdhc_writew_fixup(host, reg, val, value);
427 iowrite32be(ret, host->ioaddr + base);
437 iowrite32be(ret, host->ioaddr + base);
442 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
444 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
450 value = ioread32(host->ioaddr + base);
451 ret = esdhc_writew_fixup(host, reg, val, value);
453 iowrite32(ret, host->ioaddr + base);
463 iowrite32(ret, host->ioaddr + base);
468 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
474 value = ioread32be(host->ioaddr + base);
475 ret = esdhc_writeb_fixup(host, reg, val, value);
476 iowrite32be(ret, host->ioaddr + base);
479 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
485 value = ioread32(host->ioaddr + base);
486 ret = esdhc_writeb_fixup(host, reg, val, value);
487 iowrite32(ret, host->ioaddr + base);
497 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
499 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
511 host->data->error = 0;
512 dmastart = sg_dma_address(host->data->sg);
513 dmanow = dmastart + host->data->bytes_xfered;
519 host->data->bytes_xfered = dmanow - dmastart;
520 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
523 static int esdhc_of_enable_dma(struct sdhci_host *host)
527 struct device *dev = mmc_dev(host->mmc);
536 value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
543 sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
547 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
549 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
558 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
560 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
571 static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
573 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
588 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
595 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
605 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
609 mmc_hostname(host->mmc));
616 static void esdhc_flush_async_fifo(struct sdhci_host *host)
621 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
623 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
630 if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) &
635 mmc_hostname(host->mmc));
642 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
644 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
652 host->mmc->actual_clock = 0;
653 esdhc_clock_enable(host, false);
662 if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
663 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
666 clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
672 while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256)
675 while (host->max_clk / pre_div / div > clock_fixup && div < 16)
683 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
684 host->flags & SDHCI_HS400_TUNING)) {
696 mmc_hostname(host->mmc));
701 host->mmc->actual_clock = host->max_clk / esdhc->div_ratio;
703 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
704 clock, host->mmc->actual_clock);
710 esdhc_clock_enable(host, false);
712 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
716 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
726 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
730 mmc_hostname(host->mmc));
737 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
739 temp = sdhci_readl(host, ESDHC_TBCTL);
740 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL);
741 temp = sdhci_readl(host, ESDHC_SDCLKCTL);
742 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL);
743 esdhc_clock_enable(host, true);
745 temp = sdhci_readl(host, ESDHC_DLLCFG0);
747 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR)
749 sdhci_writel(host, temp, ESDHC_DLLCFG0);
752 sdhci_writel(host, temp, ESDHC_DLLCFG0);
755 sdhci_writel(host, temp, ESDHC_DLLCFG0);
761 host, ESDHC_DLLSTAT0))
763 mmc_hostname(host->mmc));
765 temp = sdhci_readl(host, ESDHC_TBCTL);
766 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
768 esdhc_clock_enable(host, false);
769 esdhc_flush_async_fifo(host);
771 esdhc_clock_enable(host, true);
774 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
778 ctrl = sdhci_readl(host, ESDHC_PROCTL);
793 sdhci_writel(host, ctrl, ESDHC_PROCTL);
796 static void esdhc_reset(struct sdhci_host *host, u8 mask)
798 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
808 (host->flags & SDHCI_REQ_USE_DMA))
817 val = sdhci_readl(host, ESDHC_PROCTL);
821 sdhci_reset(host, mask);
829 val = sdhci_readl(host, ESDHC_PROCTL);
832 sdhci_writel(host, val, ESDHC_PROCTL);
834 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
835 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
844 val = sdhci_readl(host, ESDHC_TBCTL);
846 sdhci_writel(host, val, ESDHC_TBCTL);
853 val = sdhci_readl(host, ESDHC_DLLCFG1);
855 sdhci_writel(host, val, ESDHC_DLLCFG1);
881 struct sdhci_host *host = mmc_priv(mmc);
891 if (host->version < SDHCI_SPEC_300)
894 val = sdhci_readl(host, ESDHC_PROCTL);
899 sdhci_writel(host, val, ESDHC_PROCTL);
913 sdhci_writel(host, val, ESDHC_PROCTL);
923 sdhci_writel(host, val, ESDHC_PROCTL);
949 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable)
953 esdhc_clock_enable(host, false);
954 esdhc_flush_async_fifo(host);
956 val = sdhci_readl(host, ESDHC_TBCTL);
961 sdhci_writel(host, val, ESDHC_TBCTL);
963 esdhc_clock_enable(host, true);
966 static void esdhc_tuning_window_ptr(struct sdhci_host *host, u8 *window_start,
972 val = sdhci_readl(host, ESDHC_TBCTL);
975 sdhci_writel(host, val, ESDHC_TBCTL);
980 val = sdhci_readl(host, ESDHC_TBCTL);
981 sdhci_writel(host, val, ESDHC_TBCTL);
986 val = sdhci_readl(host, ESDHC_TBSTAT);
987 val = sdhci_readl(host, ESDHC_TBSTAT);
993 static void esdhc_prepare_sw_tuning(struct sdhci_host *host, u8 *window_start,
996 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1006 esdhc_tuning_window_ptr(host, &start_ptr, &end_ptr);
1009 sdhci_reset(host, SDHCI_RESET_DATA);
1011 sdhci_writel(host, 0xFFFFFFFF, SDHCI_INT_STATUS);
1031 struct sdhci_host *host = mmc_priv(mmc);
1032 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1041 sdhci_writel(host, val, ESDHC_TBPTR);
1044 val = sdhci_readl(host, ESDHC_TBCTL);
1047 sdhci_writel(host, val, ESDHC_TBCTL);
1057 struct sdhci_host *host = mmc_priv(mmc);
1058 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1070 if (host->clock > clk)
1071 esdhc_of_set_clock(host, clk);
1073 esdhc_tuning_block_enable(host, true);
1084 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
1086 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1091 esdhc_of_set_clock(host, host->clock);
1094 val = sdhci_readl(host, ESDHC_TBCTL);
1097 sdhci_writel(host, val, ESDHC_TBCTL);
1108 !host->tuning_err) {
1109 esdhc_tuning_window_ptr(host, &window_start,
1113 host->tuning_err = -EAGAIN;
1119 ret = host->tuning_err;
1125 host->flags |= SDHCI_HS400_TUNING;
1129 esdhc_prepare_sw_tuning(host, &window_start,
1138 ret = host->tuning_err;
1142 host->flags |= SDHCI_HS400_TUNING;
1144 clk = host->max_clk / (esdhc->div_ratio + 1);
1145 esdhc_of_set_clock(host, clk);
1157 esdhc_tuning_block_enable(host, false);
1159 val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1161 sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
1167 static void esdhc_set_uhs_signaling(struct sdhci_host *host,
1177 val = sdhci_readl(host, ESDHC_TBCTL);
1179 val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1181 sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
1183 val = sdhci_readl(host, ESDHC_SDCLKCTL);
1185 sdhci_writel(host, val, ESDHC_SDCLKCTL);
1187 esdhc_clock_enable(host, false);
1188 val = sdhci_readl(host, ESDHC_TBCTL);
1190 sdhci_writel(host, val, ESDHC_TBCTL);
1191 esdhc_clock_enable(host, true);
1193 val = sdhci_readl(host, ESDHC_DLLCFG0);
1195 sdhci_writel(host, val, ESDHC_DLLCFG0);
1197 val = sdhci_readl(host, ESDHC_TBCTL);
1199 sdhci_writel(host, val, ESDHC_TBCTL);
1201 esdhc_tuning_block_enable(host, false);
1205 esdhc_tuning_block_enable(host, true);
1207 sdhci_set_uhs_signaling(host, timing);
1210 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask)
1212 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1217 command = SDHCI_GET_CMD(sdhci_readw(host,
1220 sdhci_readw(host, SDHCI_BLOCK_COUNT) &&
1223 sdhci_writel(host, SDHCI_INT_DATA_END,
1234 struct sdhci_host *host = dev_get_drvdata(dev);
1236 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
1238 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1239 mmc_retune_needed(host->mmc);
1241 return sdhci_suspend_host(host);
1246 struct sdhci_host *host = dev_get_drvdata(dev);
1247 int ret = sdhci_resume_host(host);
1251 esdhc_of_enable_dma(host);
1252 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
1335 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
1345 pltfm_host = sdhci_priv(host);
1348 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
1396 esdhc_clock_enable(host, false);
1397 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
1407 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
1408 esdhc_clock_enable(host, true);
1419 struct sdhci_host *host;
1428 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
1431 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
1434 if (IS_ERR(host))
1435 return PTR_ERR(host);
1437 host->mmc_host_ops.start_signal_voltage_switch =
1439 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
1440 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr;
1441 host->tuning_delay = 1;
1443 esdhc_init(pdev, host);
1447 pltfm_host = sdhci_priv(host);
1460 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
1463 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1466 host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
1467 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1475 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1478 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1484 * host control register
1486 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
1491 ret = mmc_of_parse(host->mmc);
1495 mmc_of_parse_voltage(np, &host->ocr_mask);
1497 ret = sdhci_add_host(host);