Lines Matching defs:clock
555 return pltfm_host->clock;
562 unsigned int clock;
565 clock = esdhc->peripheral_clock;
567 clock = pltfm_host->clock;
568 return clock / 256 / 16;
599 * wait clock stable bit which does not exist.
608 pr_err("%s: Internal clock never stabilised.\n",
642 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
651 if (clock == 0) {
661 /* Fix clock value. */
668 if (clock_fixup == 0 || clock < clock_fixup)
669 clock_fixup = clock;
680 /* Limit clock division for HS400 200MHz clock for quirk. */
682 clock == MMC_HS200_MAX_DTR &&
695 pr_warn("%s: using unsupported clock division.\n",
703 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
704 clock, host->mmc->actual_clock);
706 /* Set clock division into register. */
720 * wait clock stable bit which does not exist.
729 pr_err("%s: Internal clock never stabilised.\n",
738 clock == MMC_HS200_MAX_DTR) {
1066 /* For tuning mode, the sd clock divisor value
1070 if (host->clock > clk)
1091 esdhc_of_set_clock(host, host->clock);
1126 pr_info("%s: Hold on to use fixed sampling clock. Try SW tuning!\n",
1137 /* Retry both HW/SW tuning with reduced clock. */
1146 pr_info("%s: Hold on to use fixed sampling clock. Try tuning with reduced clock!\n",
1381 * which is eSDHC base clock when use periperal clock.
1382 * For some platforms, the clock value got by common clk
1383 * API is peripheral clock while the eSDHC base clock is
1384 * 1/2 peripheral clock.