Lines Matching refs:clk_xin
563 * @parent_rate: The parent rate (should be rate of clk_xin).
590 * @parent_rate: The parent rate (should be rate of clk_xin).
962 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
970 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
1288 * @clk_xin: Pointer to the functional clock
1299 struct clk *clk_xin,
1315 parent_clk_name = __clk_get_name(clk_xin);
1340 * @clk_xin: Pointer to the functional clock
1351 struct clk *clk_xin,
1367 parent_clk_name = __clk_get_name(clk_xin);
1445 * @clk_xin: Pointer to the functional clock
1463 struct clk *clk_xin,
1474 ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1479 ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1538 struct clk *clk_xin;
1579 clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
1580 if (IS_ERR(clk_xin)) {
1581 dev_err(&pdev->dev, "clk_xin clock not found.\n");
1582 ret = PTR_ERR(clk_xin);
1592 ret = clk_prepare_enable(clk_xin);
1606 pltfm_host->clk = clk_xin;
1623 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
1683 clk_disable_unprepare(clk_xin);