Lines Matching defs:clock
99 * @sdcardclk_ops: The output clock related operations
100 * @sampleclk_ops: The sample clock related operations
110 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
111 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
112 * @sampleclk_hw: Struct for the clock we might provide to a PHY.
113 * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
117 * @clk_of_data: Platform specific runtime clock data storage pointer
134 * @clk_ahb: Pointer to the AHB clock
161 * internal clock even when the clock isn't stable */
254 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
262 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
264 * If PHY off, set clock to max speed and power PHY on.
267 * when changing the clock the PHY doesn't like to be
270 * clock is off.
288 * sdhci_set_clock() will set the real clock.
290 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
292 * At higher clock speeds the PHY is fine being power
294 * changing clock speeds.
311 if (clock == DEFAULT_SPEED_MAX_DTR)
312 clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25;
319 sdhci_set_clock(host, clock);
324 * after enabling the clock even though the clock is not
325 * stable. Trying to use a clock without waiting here results
524 dev_err(dev, "Cannot enable AHB clock.\n");
530 dev_err(dev, "Cannot enable SD clock.\n");
560 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
562 * @hw: Pointer to the hardware clock structure.
565 * Return the current actual rate of the SD card clock. This can be used
568 * Return: The card clock rate.
587 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
589 * @hw: Pointer to the hardware clock structure.
592 * Return the current actual rate of the sampling clock. This can be used
595 * Return: The sample clock rate.
616 * @hw: Pointer to the hardware clock structure.
617 * @degrees: The clock phase shift between 0 - 359.
645 /* For 50MHz clock, 30 Taps are available */
649 /* For 100MHz clock, 15 Taps are available */
654 /* For 200MHz clock, 8 Taps are available */
681 * @hw: Pointer to the hardware clock structure.
682 * @degrees: The clock phase shift between 0 - 359.
713 /* For 50MHz clock, 120 Taps are available */
717 /* For 100MHz clock, 60 Taps are available */
722 /* For 200MHz clock, 30 Taps are available */
746 * @hw: Pointer to the hardware clock structure.
747 * @degrees: The clock phase shift between 0 - 359.
772 /* For 50MHz clock, 30 Taps are available */
776 /* For 100MHz clock, 15 Taps are available */
781 /* For 200MHz clock, 8 Taps are available */
812 * @hw: Pointer to the hardware clock structure.
813 * @degrees: The clock phase shift between 0 - 359.
838 /* For 50MHz clock, 120 Taps are available */
842 /* For 100MHz clock, 60 Taps are available */
847 /* For 200MHz clock, 30 Taps are available */
923 * The corecfg_clockmultiplier is supposed to contain clock multiplier
924 * value of programmable clock generator.
971 * to achieve lower clock rates. That means that this function is called once
1022 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
1288 * @clk_xin: Pointer to the functional clock
1291 * Some PHY devices need to know what the actual card clock is. In order for
1292 * them to find out, we'll provide a clock through the common clock framework
1308 ret = of_property_read_string_index(np, "clock-output-names", 0,
1311 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1331 dev_err(dev, "Failed to add sdcard clock provider\n");
1340 * @clk_xin: Pointer to the functional clock
1343 * Some PHY devices need to know what the actual card clock is. In order for
1344 * them to find out, we'll provide a clock through the common clock framework
1360 ret = of_property_read_string_index(np, "clock-output-names", 1,
1363 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1383 dev_err(dev, "Failed to add sample clock provider\n");
1400 if (!of_find_property(np, "#clock-cells", NULL))
1445 * @clk_xin: Pointer to the functional clock
1448 * Some PHY devices need to know what the actual card clock is. In order for
1449 * them to find out, we'll provide a clock through the common clock framework
1452 * Note: without seriously re-architecting SDHCI's clock code and testing on
1453 * all platforms, there's no way to create a totally beautiful clock here
1454 * with all clock ops implemented. Instead, we'll just create a clock that can
1455 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1470 /* Providing a clock to the PHY is optional; no error if missing */
1471 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1574 dev_err(&pdev->dev, "clk_ahb clock not found.\n");
1581 dev_err(&pdev->dev, "clk_xin clock not found.\n");
1588 dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
1594 dev_err(&pdev->dev, "Unable to enable SD clock.\n");
1603 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))