Lines Matching refs:phase
401 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
414 if (phase > 0xf)
430 * Write the selected DLL clock output phase (0 ... 15)
435 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
454 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
455 mmc_hostname(mmc), phase);
468 * selected DLL clock output phase.
495 /* check if next phase in phase_table is consecutive or not */
505 /* Check if phase-0 is present in first valid window? */
525 /* number of phases in raw where phase 0 is present */
527 /* number of phases in raw where phase 15 is present */
532 * If there are more than 1 phase windows then total
566 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
894 * tuning block and restore the saved tuning phase.
900 /* Set the selected phase in delay line hw block */
1074 * tuning block and restore the saved tuning phase.
1081 /* Set the selected phase in delay line hw block */
1170 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1208 phase = 0;
1210 /* Set the phase in delay line hw block */
1211 rc = msm_config_cm_dll_phase(host, phase);
1218 tuned_phases[tuned_phase_cnt++] = phase;
1219 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1220 mmc_hostname(mmc), phase);
1222 } while (++phase < ARRAY_SIZE(tuned_phases));
1231 * we get a good phase. Better to try a few times.
1246 phase = rc;
1249 * Finally set the selected phase in delay
1252 rc = msm_config_cm_dll_phase(host, phase);
1255 msm_host->saved_tuning_phase = phase;
1256 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1257 mmc_hostname(mmc), phase);