Lines Matching refs:msm_offset
379 const struct sdhci_msm_offset *msm_offset =
384 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
395 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
411 const struct sdhci_msm_offset *msm_offset =
419 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
422 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
433 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
436 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
438 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
440 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
447 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
450 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
576 const struct sdhci_msm_offset *msm_offset =
597 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
600 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
612 const struct sdhci_msm_offset *msm_offset =
625 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
627 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
631 host->ioaddr + msm_offset->core_dll_config);
635 msm_offset->core_dll_config);
638 msm_offset->core_dll_config);
641 msm_offset->core_dll_config_2);
644 msm_offset->core_dll_config_2);
648 msm_offset->core_dll_config);
651 msm_offset->core_dll_config);
654 msm_offset->core_dll_config);
657 msm_offset->core_dll_config);
667 msm_offset->core_dll_config_2);
677 msm_offset->core_dll_config_2);
682 msm_offset->core_dll_config_2);
688 msm_offset->core_dll_config);
691 msm_offset->core_dll_config);
694 msm_offset->core_dll_config);
697 msm_offset->core_dll_config);
703 msm_offset->core_dll_config_2);
706 msm_offset->core_dll_config_2);
717 msm_offset->core_dll_usr_ctl);
720 msm_offset->core_dll_config_3);
727 msm_offset->core_dll_config_3);
731 msm_offset->core_dll_config);
734 msm_offset->core_dll_config);
737 msm_offset->core_dll_config);
740 msm_offset->core_dll_config);
743 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
764 const struct sdhci_msm_offset *msm_offset =
769 msm_offset->core_vendor_spec3);
772 msm_offset->core_vendor_spec3);
775 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
778 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
787 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
790 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
806 const struct sdhci_msm_offset *msm_offset =
810 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
814 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
822 msm_offset->core_vendor_spec);
826 msm_offset->core_vendor_spec);
835 msm_offset->core_dll_status,
887 const struct sdhci_msm_offset *msm_offset =
905 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
907 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
909 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
911 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
921 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
923 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
975 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
977 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
991 const struct sdhci_msm_offset *msm_offset =
1004 ddr_cfg_offset = msm_offset->core_ddr_config;
1006 ddr_cfg_offset = msm_offset->core_ddr_config_old;
1011 msm_offset->core_ddr_200_cfg);
1014 msm_offset->core_ddr_200_cfg);
1017 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
1019 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
1022 msm_offset->core_dll_status,
1043 msm_offset->core_vendor_spec3);
1046 msm_offset->core_vendor_spec3);
1067 const struct sdhci_msm_offset *msm_offset =
1087 msm_offset->core_dll_config);
1090 msm_offset->core_dll_config);
1147 const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1149 msm_offset->core_dll_config);
1162 msm_offset->core_dll_config);
1304 const struct sdhci_msm_offset *msm_offset =
1347 msm_offset->core_dll_config);
1350 msm_offset->core_dll_config);
1353 msm_offset->core_dll_config);
1356 msm_offset->core_dll_config);
1501 const struct sdhci_msm_offset *msm_offset =
1516 msm_offset->core_generics);
1564 const struct sdhci_msm_offset *msm_offset =
1569 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1570 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1571 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1583 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1586 msm_offset->core_pwrctl_status);
1590 msm_offset->core_pwrctl_clear);
1600 msm_offset->core_pwrctl_status)) {
1609 msm_offset->core_pwrctl_clear);
1665 msm_offset->core_pwrctl_ctl);
1685 msm_offset->core_vendor_spec);
1697 msm_offset->core_vendor_spec);
2009 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2030 msm_offset->core_vendor_spec);
2039 host->ioaddr + msm_offset->core_vendor_spec);
2125 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2131 readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
2132 readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
2133 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
2136 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
2137 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
2138 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
2141 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
2143 msm_offset->core_vendor_spec_func2),
2144 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
2284 const struct sdhci_msm_offset *msm_offset;
2314 msm_offset = msm_host->offset;
2413 host->ioaddr + msm_offset->core_vendor_spec);
2418 msm_offset->core_hc_mode);
2420 msm_offset->core_hc_mode);
2423 msm_offset->core_hc_mode);
2432 msm_offset->core_mci_version);
2457 msm_offset->core_vendor_spec_capabilities0);
2492 msm_offset->core_pwrctl_mask);