Lines Matching refs:msm_host
137 #define msm_host_readl(msm_host, host, offset) \
138 msm_host->var_ops->msm_readl_relaxed(host, offset)
140 #define msm_host_writel(msm_host, val, host, offset) \
141 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
293 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
295 return msm_host->offset;
306 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
308 return readl_relaxed(msm_host->core_mem + offset);
321 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
323 writel_relaxed(val, msm_host->core_mem + offset);
354 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
356 struct clk *core_clk = msm_host->bulk_clks[0].clk;
367 msm_host->clk_rate = clock;
608 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
613 msm_host->offset;
615 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
616 xo_clk = clk_get_rate(msm_host->xo_clk);
629 if (msm_host->dll_config)
630 writel_relaxed(msm_host->dll_config,
633 if (msm_host->use_14lpp_dll_reset) {
659 if (!msm_host->dll_config)
662 if (msm_host->use_14lpp_dll_reset &&
663 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
699 if (msm_host->use_14lpp_dll_reset) {
700 if (!msm_host->dll_config)
713 if (msm_host->uses_tassadar_dll) {
722 if (msm_host->clk_rate < 150000000)
762 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
765 msm_host->offset;
767 if (!msm_host->use_cdclp533) {
802 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
807 msm_host->offset;
819 if ((msm_host->tuning_done || ios.enhanced_strobe) &&
820 !msm_host->calibration_done) {
828 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
884 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
888 msm_host->offset;
901 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
990 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1003 if (msm_host->updated_ddr_cfg)
1007 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
1041 if (!msm_host->use_14lpp_dll_reset) {
1063 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1068 msm_host->offset;
1083 msm_host->saved_tuning_phase);
1093 if (msm_host->use_cdclp533)
1124 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1140 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1174 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1177 msm_host->use_cdr = false;
1183 msm_host->use_cdr = true;
1189 msm_host->tuning_done = 0;
1255 msm_host->saved_tuning_phase = phase;
1268 msm_host->tuning_done = true;
1281 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1285 (msm_host->tuning_done || ios->enhanced_strobe) &&
1286 !msm_host->calibration_done) {
1289 msm_host->calibration_done = true;
1301 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1305 msm_host->offset;
1362 msm_host->calibration_done = false;
1373 static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)
1375 struct platform_device *pdev = msm_host->pdev;
1394 static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,
1400 if (msm_host->vqmmc_enabled == level)
1405 if (msm_host->caps_0 & CORE_3_0V_SUPPORT)
1407 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)
1410 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1427 msm_host->vqmmc_enabled = level;
1432 static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,
1445 static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,
1468 ret = msm_config_vqmmc_mode(msm_host, mmc, level);
1470 ret = msm_toggle_vqmmc(msm_host, mmc, level);
1475 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1477 init_waitqueue_head(&msm_host->pwr_irq_wait);
1481 struct sdhci_msm_host *msm_host)
1483 wake_up(&msm_host->pwr_irq_wait);
1498 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1502 msm_host->offset;
1506 msm_host->curr_pwr_state, msm_host->curr_io_level);
1514 if (!msm_host->mci_removed)
1515 val = msm_host_readl(msm_host, host,
1539 if ((req_type & msm_host->curr_pwr_state) ||
1540 (req_type & msm_host->curr_io_level))
1549 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1550 msm_host->pwr_irq_flag,
1552 dev_warn(&msm_host->pdev->dev,
1563 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1565 msm_host->offset;
1569 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1570 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1571 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1577 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1583 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1585 irq_status = msm_host_readl(msm_host, host,
1589 msm_host_writel(msm_host, irq_status, host,
1599 while (irq_status & msm_host_readl(msm_host, host,
1608 msm_host_writel(msm_host, irq_status, host,
1627 ret = sdhci_msm_set_vqmmc(msm_host, mmc,
1630 ret = sdhci_msm_set_pincfg(msm_host,
1664 msm_host_writel(msm_host, irq_ack, host,
1671 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1689 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1692 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1701 msm_host->curr_pwr_state = pwr_state;
1703 msm_host->curr_io_level = io_level;
1706 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1714 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1717 msm_host->pwr_irq_flag = 1;
1718 sdhci_msm_complete_pwr_irq_wait(msm_host);
1727 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1728 struct clk *core_clk = msm_host->bulk_clks[0].clk;
1775 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1778 msm_host->clk_rate = clock;
1864 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1888 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1937 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1953 msm_host->transfer_mode = val;
1956 if (!msm_host->use_cdr)
1958 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
1968 msm_host->pwr_irq_flag = 0;
2003 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
2005 struct mmc_host *mmc = msm_host->mmc;
2009 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2027 u32 io_level = msm_host->curr_io_level;
2041 msm_host->caps_0 |= caps;
2052 static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)
2056 ret = mmc_regulator_get_supply(msm_host->mmc);
2060 sdhci_msm_set_regulator_caps(msm_host);
2124 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2125 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2224 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2227 &msm_host->ddr_config))
2228 msm_host->ddr_config = DDR_CONFIG_POR_VAL;
2230 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
2278 struct sdhci_msm_host *msm_host;
2288 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
2294 msm_host = sdhci_pltfm_priv(pltfm_host);
2295 msm_host->mmc = host->mmc;
2296 msm_host->pdev = pdev;
2308 msm_host->mci_removed = var_info->mci_removed;
2309 msm_host->restore_dll_config = var_info->restore_dll_config;
2310 msm_host->var_ops = var_info->var_ops;
2311 msm_host->offset = var_info->offset;
2312 msm_host->uses_tassadar_dll = var_info->uses_tassadar_dll;
2314 msm_offset = msm_host->offset;
2319 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
2326 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
2327 if (!IS_ERR(msm_host->bus_clk)) {
2329 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
2332 ret = clk_prepare_enable(msm_host->bus_clk);
2344 msm_host->bulk_clks[1].clk = clk;
2353 msm_host->bulk_clks[0].clk = clk;
2360 msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core");
2361 if (IS_ERR(msm_host->opp_table)) {
2362 ret = PTR_ERR(msm_host->opp_table);
2381 msm_host->bulk_clks[2].clk = clk;
2386 msm_host->bulk_clks[3].clk = clk;
2388 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2389 msm_host->bulk_clks);
2397 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
2398 if (IS_ERR(msm_host->xo_clk)) {
2399 ret = PTR_ERR(msm_host->xo_clk);
2403 if (!msm_host->mci_removed) {
2404 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);
2405 if (IS_ERR(msm_host->core_mem)) {
2406 ret = PTR_ERR(msm_host->core_mem);
2415 if (!msm_host->mci_removed) {
2417 msm_host_writel(msm_host, HC_MODE_EN, host,
2419 config = msm_host_readl(msm_host, host,
2422 msm_host_writel(msm_host, config, host,
2431 core_version = msm_host_readl(msm_host, host,
2440 msm_host->use_14lpp_dll_reset = true;
2447 msm_host->use_cdclp533 = true;
2461 msm_host->updated_ddr_cfg = true;
2463 ret = sdhci_msm_register_vreg(msm_host);
2483 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
2484 if (msm_host->pwr_irq < 0) {
2485 ret = msm_host->pwr_irq;
2489 sdhci_msm_init_pwr_irq_wait(msm_host);
2491 msm_host_writel(msm_host, INT_MASK, host,
2494 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
2502 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
2531 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2532 msm_host->bulk_clks);
2536 dev_pm_opp_put_clkname(msm_host->opp_table);
2538 if (!IS_ERR(msm_host->bus_clk))
2539 clk_disable_unprepare(msm_host->bus_clk);
2549 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2556 dev_pm_opp_put_clkname(msm_host->opp_table);
2561 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2562 msm_host->bulk_clks);
2563 if (!IS_ERR(msm_host->bus_clk))
2564 clk_disable_unprepare(msm_host->bus_clk);
2573 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2577 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2578 msm_host->bulk_clks);
2587 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2590 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2591 msm_host->bulk_clks);
2598 if (msm_host->restore_dll_config && msm_host->clk_rate)
2601 dev_pm_opp_set_rate(dev, msm_host->clk_rate);