Lines Matching defs:new_val
588 u32 new_val = 0;
592 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
594 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
596 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
597 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
598 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
602 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
604 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
606 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
607 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
609 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
611 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
612 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
614 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
615 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
617 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
744 u32 new_val = 0;
756 new_val = val & SDHCI_CTRL_LED;
758 new_val |= ESDHC_HOST_CONTROL_LE;
762 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
773 esdhc_clrset_le(host, mask, new_val, reg);
777 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
802 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
803 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
813 esdhc_clrset_le(host, 0xff, new_val,