Lines Matching defs:host
20 #include <linux/mmc/host.h>
337 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
339 void __iomem *base = host->ioaddr + (reg & ~0x3);
347 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
348 static void esdhc_dump_debug_regs(struct sdhci_host *host)
363 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
366 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
369 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
373 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
378 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
381 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
384 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
386 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
388 u32 val = readl(host->ioaddr + reg);
421 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
464 writel(SDHCI_INT_RESPONSE, host->ioaddr +
473 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
475 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
490 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
492 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
494 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
507 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
509 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
516 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
521 writel(val, host->ioaddr + reg);
524 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
526 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
535 * The usdhc register returns a wrong host version.
543 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
549 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
552 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
567 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
575 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
581 return readw(host->ioaddr + reg);
584 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
586 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
592 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
597 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
599 esdhc_wait_for_card_clock_gate_off(host);
602 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
607 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
609 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
617 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
619 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
620 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
637 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
638 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
643 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
644 && (host->cmd->data->blocks > 1)
645 && (host->cmd->data->flags & MMC_DATA_READ)) {
647 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
649 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
654 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
661 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
667 m = readl(host->ioaddr + ESDHC_WTMK_LVL);
682 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
684 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
690 writel(m, host->ioaddr + ESDHC_WTMK_LVL);
700 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
703 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
709 host->ioaddr + SDHCI_TRANSFER_MODE);
712 host->ioaddr + SDHCI_TRANSFER_MODE);
718 esdhc_clrset_le(host, 0xffff, val, reg);
721 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
728 val = readl(host->ioaddr + reg);
737 return readb(host->ioaddr + reg);
740 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
742 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
773 esdhc_clrset_le(host, mask, new_val, reg);
777 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
780 esdhc_clrset_le(host, 0xff, val, reg);
793 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
802 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
804 host->ioaddr + ESDHC_MIX_CTRL);
813 esdhc_clrset_le(host, 0xff, new_val,
819 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
821 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
826 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
828 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
833 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
836 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
846 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
848 host->ioaddr + ESDHC_VENDOR_SPEC);
849 esdhc_wait_for_card_clock_gate_off(host);
853 host->mmc->actual_clock = 0;
863 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
864 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
865 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
866 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
871 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
874 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
877 (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V))) {
892 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
893 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
894 clock, host->mmc->actual_clock);
899 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
903 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
906 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
909 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
912 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
914 host->ioaddr + ESDHC_VENDOR_SPEC);
919 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
921 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
927 return mmc_gpio_get_ro(host->mmc);
929 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
938 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
954 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
960 struct sdhci_host *host = mmc_priv(mmc);
966 if (host->timing == MMC_TIMING_UHS_DDR50)
972 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
982 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
983 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
986 dev_warn(mmc_dev(host->mmc),
989 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
992 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
993 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
994 dev_dbg(mmc_dev(host->mmc),
996 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
999 static void esdhc_post_tuning(struct sdhci_host *host)
1003 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1006 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1009 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1016 esdhc_prepare_tuning(host, min);
1017 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1025 esdhc_prepare_tuning(host, max);
1026 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1035 esdhc_prepare_tuning(host, avg);
1036 ret = mmc_send_tuning(host->mmc, opcode, NULL);
1037 esdhc_post_tuning(host);
1039 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1047 struct sdhci_host *host = mmc_priv(mmc);
1050 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1055 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1058 static int esdhc_change_pinstate(struct sdhci_host *host,
1061 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1065 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1084 return pinctrl_select_default_state(mmc_dev(host->mmc));
1094 * CLK generated by host. The host receives the data which is aligned to the
1099 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1101 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1108 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1110 host->ioaddr + ESDHC_VENDOR_SPEC);
1111 esdhc_wait_for_card_clock_gate_off(host);
1115 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1117 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1130 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1133 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1136 dev_warn(mmc_dev(host->mmc),
1140 static void esdhc_reset_tuning(struct sdhci_host *host)
1142 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1150 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1153 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1154 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1156 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1159 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1161 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
1164 dev_warn(mmc_dev(host->mmc),
1171 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
1173 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
1178 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1181 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1186 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1197 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1202 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1211 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1216 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1219 host->ops->set_clock(host, host->clock);
1220 esdhc_set_strobe_dll(host);
1224 esdhc_reset_tuning(host);
1228 esdhc_change_pinstate(host, timing);
1231 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1233 sdhci_and_cqhci_reset(host, mask);
1235 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1236 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1239 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1241 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1248 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1250 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1254 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1259 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1264 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1267 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1300 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1302 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1304 struct cqhci_host *cq_host = host->mmc->cqe_private;
1312 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1325 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1327 host->ioaddr + SDHCI_HOST_CONTROL);
1333 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1334 host->ioaddr + 0x6c);
1337 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1349 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1351 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1353 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1357 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1389 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1396 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1398 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1420 struct sdhci_host *host = mmc_priv(mmc);
1430 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1432 sdhci_readl(host, SDHCI_BUFFER);
1433 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1435 dev_warn(mmc_dev(host->mmc),
1443 * Runtime resume will reset the entire host controller, which
1447 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1448 if (host->flags & SDHCI_REQ_USE_DMA)
1450 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1452 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1455 * Though Runtime resume reset the entire host controller,
1462 dev_err(mmc_dev(host->mmc),
1483 struct sdhci_host *host,
1508 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1513 mmc_of_parse_voltage(np, &host->ocr_mask);
1523 ret = mmc_of_parse(host->mmc);
1527 if (mmc_gpio_get_cd(host->mmc) >= 0)
1528 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1535 struct sdhci_host *host,
1547 struct sdhci_host *host;
1552 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1554 if (IS_ERR(host))
1555 return PTR_ERR(host);
1557 pltfm_host = sdhci_priv(host);
1598 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1601 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1602 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1605 host->mmc->caps |= MMC_CAP_CD_WAKE;
1608 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1611 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1612 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1613 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1619 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1622 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1631 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1633 if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1635 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1638 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1640 if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1642 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1643 host->mmc_host_ops.hs400_enhanced_strobe =
1648 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1655 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1658 err = cqhci_init(cq_host, host->mmc, false);
1663 sdhci_esdhc_imx_hwinit(host);
1665 err = sdhci_add_host(host);
1692 struct sdhci_host *host = platform_get_drvdata(pdev);
1693 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1698 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1702 sdhci_remove_host(host, dead);
1719 struct sdhci_host *host = dev_get_drvdata(dev);
1720 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1724 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1725 ret = cqhci_suspend(host->mmc);
1731 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1732 mmc_retune_timer_stop(host->mmc);
1733 mmc_retune_needed(host->mmc);
1736 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1737 mmc_retune_needed(host->mmc);
1739 ret = sdhci_suspend_host(host);
1747 ret = mmc_gpio_set_cd_wake(host->mmc, true);
1754 struct sdhci_host *host = dev_get_drvdata(dev);
1762 sdhci_esdhc_imx_hwinit(host);
1764 ret = sdhci_resume_host(host);
1768 if (host->mmc->caps2 & MMC_CAP2_CQE)
1769 ret = cqhci_resume(host->mmc);
1772 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1781 struct sdhci_host *host = dev_get_drvdata(dev);
1782 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1786 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1787 ret = cqhci_suspend(host->mmc);
1792 ret = sdhci_runtime_suspend_host(host);
1796 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1797 mmc_retune_needed(host->mmc);
1799 imx_data->actual_clock = host->mmc->actual_clock;
1800 esdhc_pltfm_set_clock(host, 0);
1813 struct sdhci_host *host = dev_get_drvdata(dev);
1814 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1836 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1838 err = sdhci_runtime_resume_host(host, 0);
1842 if (host->mmc->caps2 & MMC_CAP2_CQE)
1843 err = cqhci_resume(host->mmc);