Lines Matching defs:host
28 #include <linux/mmc/host.h>
72 struct sdhci_host *host;
206 static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
210 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
212 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
216 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
364 struct sdhci_host *host = mmc_priv(mmc);
371 spin_lock_irqsave(&host->lock, flags);
373 if (host->flags & SDHCI_DEVICE_DEAD)
376 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
378 spin_unlock_irqrestore(&host->lock, flags);
387 struct sdhci_host *host = c->host;
390 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
391 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
392 host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
395 host->mmc_host_ops.get_cd = bxt_get_cd;
397 intel_dsm_init(intel_host, &pdev->dev, host->mmc);
399 host->mmc_host_ops.start_signal_voltage_switch =
413 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
416 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
419 c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
422 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
474 struct sdhci_host *host = ptr;
476 sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG);
477 sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG);
485 struct sdhci_host *host = c->host;
499 "sdhci_qcom", host);
506 struct sdhci_host *host = c->host;
520 free_irq(*irq, host);
554 static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host, bool enable)
556 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
560 sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
563 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
583 struct sdhci_host *host = mmc_priv(mmc);
584 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
586 unsigned int old_timing = host->timing;
591 if (old_timing != host->timing && amd_host->tuned_clock) {
592 if (host->timing == MMC_TIMING_MMC_HS400 ||
593 host->timing == MMC_TIMING_MMC_HS200) {
594 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
596 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
598 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
600 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
604 if (host->timing == MMC_TIMING_MMC_HS400 &&
606 sdhci_acpi_amd_hs400_dll(host, true);
613 struct sdhci_host *host = mmc_priv(mmc);
614 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
621 if (!err && !host->tuning_err)
627 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
629 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
634 sdhci_acpi_amd_hs400_dll(host, false);
637 sdhci_reset(host, mask);
655 struct sdhci_host *host = c->host;
657 sdhci_read_caps(host);
658 if (host->caps1 & SDHCI_SUPPORT_DDR50)
659 host->mmc->caps = MMC_CAP_1_8V_DDR;
661 if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
662 (host->mmc->caps & MMC_CAP_1_8V_DDR))
663 host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
700 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
702 host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
703 host->mmc_host_ops.set_ios = amd_set_ios;
704 host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning;
823 struct sdhci_host *host;
863 host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
864 if (IS_ERR(host))
865 return PTR_ERR(host);
867 c = sdhci_priv(host);
868 c->host = host;
875 host->hw_name = "ACPI";
876 host->ops = &sdhci_acpi_ops_dflt;
877 host->irq = platform_get_irq(pdev, 0);
878 if (host->irq < 0) {
879 err = host->irq;
883 host->ioaddr = devm_ioremap(dev, iomem->start,
885 if (host->ioaddr == NULL) {
897 host->ops = c->slot->chip->ops;
898 host->quirks |= c->slot->chip->quirks;
899 host->quirks2 |= c->slot->chip->quirks2;
900 host->mmc->caps |= c->slot->chip->caps;
901 host->mmc->caps2 |= c->slot->chip->caps2;
902 host->mmc->pm_caps |= c->slot->chip->pm_caps;
904 host->quirks |= c->slot->quirks;
905 host->quirks2 |= c->slot->quirks2;
906 host->mmc->caps |= c->slot->caps;
907 host->mmc->caps2 |= c->slot->caps2;
908 host->mmc->pm_caps |= c->slot->pm_caps;
911 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
916 err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0);
928 host->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
931 err = sdhci_setup_host(host);
941 err = __sdhci_add_host(host);
958 sdhci_cleanup_host(c->host);
963 sdhci_free_host(c->host);
982 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
983 sdhci_remove_host(c->host, dead);
988 sdhci_free_host(c->host);
997 struct sdhci_host *host = c->host;
1000 host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) {
1014 struct sdhci_host *host = c->host;
1017 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1018 mmc_retune_needed(host->mmc);
1020 ret = sdhci_suspend_host(host);
1034 return sdhci_resume_host(c->host);
1044 struct sdhci_host *host = c->host;
1047 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1048 mmc_retune_needed(host->mmc);
1050 ret = sdhci_runtime_suspend_host(host);
1064 return sdhci_runtime_resume_host(c->host, 0);