Lines Matching refs:host
15 #include <linux/mmc/host.h>
130 #define dbg(host, channels, args...) \
133 dev_err(&host->pdev->dev, args); \
135 dev_info(&host->pdev->dev, args); \
137 dev_dbg(&host->pdev->dev, args); \
140 static void finalize_request(struct s3cmci_host *host);
142 static void s3cmci_reset(struct s3cmci_host *host);
146 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
151 con = readl(host->base + S3C2410_SDICON);
152 pre = readl(host->base + S3C2410_SDIPRE);
153 cmdarg = readl(host->base + S3C2410_SDICMDARG);
154 cmdcon = readl(host->base + S3C2410_SDICMDCON);
155 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
156 r0 = readl(host->base + S3C2410_SDIRSP0);
157 r1 = readl(host->base + S3C2410_SDIRSP1);
158 r2 = readl(host->base + S3C2410_SDIRSP2);
159 r3 = readl(host->base + S3C2410_SDIRSP3);
160 timer = readl(host->base + S3C2410_SDITIMER);
161 datcon = readl(host->base + S3C2410_SDIDCON);
162 datcnt = readl(host->base + S3C2410_SDIDCNT);
163 datsta = readl(host->base + S3C2410_SDIDSTA);
164 fsta = readl(host->base + S3C2410_SDIFSTA);
166 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
169 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
172 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
176 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
181 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
184 snprintf(host->dbgmsg_cmd, 300,
186 host->ccnt, (stop ? " (STOP)" : ""),
190 snprintf(host->dbgmsg_dat, 300,
192 host->dcnt, cmd->data->blksz,
196 host->dbgmsg_dat[0] = '\0';
200 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
209 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
210 host->dbgmsg_cmd, cmd->resp[0]);
212 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
213 cmd->error, host->dbgmsg_cmd, host->status);
220 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
222 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
223 cmd->data->error, host->dbgmsg_dat,
224 readl(host->base + S3C2410_SDIDCNT));
228 static void dbg_dumpcmd(struct s3cmci_host *host,
231 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
234 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
239 * s3cmci_host_usedma - return whether the host is using dma or pio
240 * @host: The host state
242 * Return true if the host is using DMA to transfer data, else false
246 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
255 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
259 newmask = readl(host->base + host->sdiimsk);
262 writel(newmask, host->base + host->sdiimsk);
267 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
271 newmask = readl(host->base + host->sdiimsk);
274 writel(newmask, host->base + host->sdiimsk);
279 static inline void clear_imask(struct s3cmci_host *host)
281 u32 mask = readl(host->base + host->sdiimsk);
285 writel(mask, host->base + host->sdiimsk);
290 * @host: The host to check.
300 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
302 if (host->sdio_irqen) {
303 if (host->pdata->bus[3] &&
304 gpiod_get_value(host->pdata->bus[3]) == 0) {
306 mmc_signal_sdio_irq(host->mmc);
311 static inline int get_data_buffer(struct s3cmci_host *host,
316 if (host->pio_active == XFER_NONE)
319 if ((!host->mrq) || (!host->mrq->data))
322 if (host->pio_sgptr >= host->mrq->data->sg_len) {
323 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
324 host->pio_sgptr, host->mrq->data->sg_len);
327 sg = &host->mrq->data->sg[host->pio_sgptr];
332 host->pio_sgptr++;
334 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
335 host->pio_sgptr, host->mrq->data->sg_len);
340 static inline u32 fifo_count(struct s3cmci_host *host)
342 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
348 static inline u32 fifo_free(struct s3cmci_host *host)
350 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
358 * @host: The device state.
369 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
376 host->irq_enabled = more;
377 host->irq_disabled = false;
379 enable = more | host->sdio_irqen;
381 if (host->irq_state != enable) {
382 host->irq_state = enable;
385 enable_irq(host->irq);
387 disable_irq(host->irq);
393 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
401 host->irq_disabled = transfer;
403 if (transfer && host->irq_state) {
404 host->irq_state = false;
405 disable_irq(host->irq);
411 static void do_pio_read(struct s3cmci_host *host)
419 /* write real prescaler to host, it might be set slow to fix */
420 writel(host->prescaler, host->base + S3C2410_SDIPRE);
422 from_ptr = host->base + host->sdidata;
424 while ((fifo = fifo_count(host))) {
425 if (!host->pio_bytes) {
426 res = get_data_buffer(host, &host->pio_bytes,
427 &host->pio_ptr);
429 host->pio_active = XFER_NONE;
430 host->complete_what = COMPLETION_FINALIZE;
432 dbg(host, dbg_pio, "pio_read(): "
437 dbg(host, dbg_pio,
439 host->pio_bytes, host->pio_ptr);
442 dbg(host, dbg_pio,
444 fifo, host->pio_bytes,
445 readl(host->base + S3C2410_SDIDCNT));
452 if (fifo >= host->pio_bytes)
453 fifo = host->pio_bytes;
457 host->pio_bytes -= fifo;
458 host->pio_count += fifo;
461 ptr = host->pio_ptr;
464 host->pio_ptr = ptr;
469 u8 *p = (u8 *)host->pio_ptr;
478 if (!host->pio_bytes) {
479 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
481 dbg(host, dbg_pio,
483 host->pio_active = XFER_NONE;
484 host->complete_what = COMPLETION_FINALIZE;
490 enable_imask(host,
494 static void do_pio_write(struct s3cmci_host *host)
501 to_ptr = host->base + host->sdidata;
503 while ((fifo = fifo_free(host)) > 3) {
504 if (!host->pio_bytes) {
505 res = get_data_buffer(host, &host->pio_bytes,
506 &host->pio_ptr);
508 dbg(host, dbg_pio,
510 host->pio_active = XFER_NONE;
515 dbg(host, dbg_pio,
517 host->pio_bytes, host->pio_ptr);
525 if (fifo >= host->pio_bytes)
526 fifo = host->pio_bytes;
530 host->pio_bytes -= fifo;
531 host->pio_count += fifo;
534 ptr = host->pio_ptr;
537 host->pio_ptr = ptr;
540 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
545 struct s3cmci_host *host = (struct s3cmci_host *) data;
547 s3cmci_disable_irq(host, true);
549 if (host->pio_active == XFER_WRITE)
550 do_pio_write(host);
552 if (host->pio_active == XFER_READ)
553 do_pio_read(host);
555 if (host->complete_what == COMPLETION_FINALIZE) {
556 clear_imask(host);
557 if (host->pio_active != XFER_NONE) {
558 dbg(host, dbg_err, "unfinished %s "
560 (host->pio_active == XFER_READ) ? "read" : "write",
561 host->pio_count, host->pio_bytes);
563 if (host->mrq->data)
564 host->mrq->data->error = -EINVAL;
567 s3cmci_enable_irq(host, false);
568 finalize_request(host);
570 s3cmci_enable_irq(host, true);
576 * host->mrq points to current request
577 * host->complete_what Indicates when the request is considered done
582 * host->complete_request is the completion-object the driver waits for
584 * 1) Driver sets up host->mrq and host->complete_what
588 * 5) Driver waits for host->complete_rquest
590 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
591 * 7) ISR completes host->complete_request
602 struct s3cmci_host *host = dev_id;
608 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
609 mci_imsk = readl(host->base + host->sdiimsk);
614 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
616 mmc_signal_sdio_irq(host->mmc);
621 spin_lock_irqsave(&host->complete_lock, iflags);
623 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
624 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
625 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
628 if ((host->complete_what == COMPLETION_NONE) ||
629 (host->complete_what == COMPLETION_FINALIZE)) {
630 host->status = "nothing to complete";
631 clear_imask(host);
635 if (!host->mrq) {
636 host->status = "no active mrq";
637 clear_imask(host);
641 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
644 host->status = "no active cmd";
645 clear_imask(host);
649 if (!s3cmci_host_usedma(host)) {
650 if ((host->pio_active == XFER_WRITE) &&
653 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
654 tasklet_schedule(&host->pio_tasklet);
655 host->status = "pio tx";
658 if ((host->pio_active == XFER_READ) &&
661 disable_imask(host,
665 tasklet_schedule(&host->pio_tasklet);
666 host->status = "pio rx";
671 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
673 host->status = "error: command timeout";
678 if (host->complete_what == COMPLETION_CMDSENT) {
679 host->status = "ok: command sent";
688 if (host->mrq->cmd->flags & MMC_RSP_136) {
689 dbg(host, dbg_irq,
697 * host->status = "error: bad command crc";
707 if (host->complete_what == COMPLETION_RSPFIN) {
708 host->status = "ok: command response received";
712 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
713 host->complete_what = COMPLETION_XFERFINISH;
725 if (host->is2440) {
727 dbg(host, dbg_err, "FIFO failure\n");
728 host->mrq->data->error = -EILSEQ;
729 host->status = "error: 2440 fifo failure";
734 dbg(host, dbg_err, "FIFO failure\n");
736 host->status = "error: fifo failure";
742 dbg(host, dbg_err, "bad data crc (outgoing)\n");
744 host->status = "error: bad data crc (outgoing)";
749 dbg(host, dbg_err, "bad data crc (incoming)\n");
751 host->status = "error: bad data crc (incoming)";
756 dbg(host, dbg_err, "data timeout\n");
758 host->status = "error: data timeout";
763 if (host->complete_what == COMPLETION_XFERFINISH) {
764 host->status = "ok: data transfer completed";
768 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
769 host->complete_what = COMPLETION_RSPFIN;
775 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
776 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
781 host->pio_active = XFER_NONE;
784 host->complete_what = COMPLETION_FINALIZE;
786 clear_imask(host);
787 tasklet_schedule(&host->pio_tasklet);
792 dbg(host, dbg_irq,
794 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
796 spin_unlock_irqrestore(&host->complete_lock, iflags);
803 struct s3cmci_host *host = arg;
806 BUG_ON(!host->mrq);
807 BUG_ON(!host->mrq->data);
809 spin_lock_irqsave(&host->complete_lock, iflags);
811 dbg(host, dbg_dma, "DMA FINISHED\n");
813 host->dma_complete = 1;
814 host->complete_what = COMPLETION_FINALIZE;
816 tasklet_schedule(&host->pio_tasklet);
817 spin_unlock_irqrestore(&host->complete_lock, iflags);
821 static void finalize_request(struct s3cmci_host *host)
823 struct mmc_request *mrq = host->mrq;
827 if (host->complete_what != COMPLETION_FINALIZE)
832 cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
836 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
837 dbg(host, dbg_dma, "DMA Missing (%d)!\n",
838 host->dma_complete);
844 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
845 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
846 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
847 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
849 writel(host->prescaler, host->base + S3C2410_SDIPRE);
857 dbg_dumpcmd(host, cmd, debug_as_failure);
860 writel(0, host->base + S3C2410_SDICMDARG);
861 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
862 writel(0, host->base + S3C2410_SDICMDCON);
863 clear_imask(host);
868 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
869 host->cmd_is_stop = 1;
870 s3cmci_send_request(host->mmc);
889 if (s3cmci_host_usedma(host))
890 dmaengine_terminate_all(host->dma);
892 if (host->is2440) {
896 host->base + S3C2410_SDIFSTA);
901 mci_con = readl(host->base + S3C2410_SDICON);
904 writel(mci_con, host->base + S3C2410_SDICON);
909 host->complete_what = COMPLETION_NONE;
910 host->mrq = NULL;
912 s3cmci_check_sdio_irq(host);
913 mmc_request_done(host->mmc, mrq);
916 static void s3cmci_send_command(struct s3cmci_host *host,
925 enable_imask(host, imsk);
928 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
930 host->complete_what = COMPLETION_RSPFIN;
932 host->complete_what = COMPLETION_CMDSENT;
934 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
945 writel(ccon, host->base + S3C2410_SDICMDCON);
948 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
963 while (readl(host->base + S3C2410_SDIDSTA) &
966 dbg(host, dbg_err,
969 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
970 s3cmci_reset(host);
973 dbg_dumpregs(host, "DRF");
980 if (s3cmci_host_usedma(host))
983 if (host->bus_width == MMC_BUS_WIDTH_4)
998 if (host->is2440) {
1003 writel(dcon, host->base + S3C2410_SDIDCON);
1007 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1013 enable_imask(host, imsk);
1017 if (host->is2440) {
1018 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1020 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1024 writel(0xFF, host->base + S3C2410_SDIPRE);
1032 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1038 host->pio_sgptr = 0;
1039 host->pio_bytes = 0;
1040 host->pio_count = 0;
1041 host->pio_active = rw ? XFER_WRITE : XFER_READ;
1044 do_pio_write(host);
1045 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1047 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1054 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1059 .src_addr = host->mem->start + host->sdidata,
1060 .dst_addr = host->mem->start + host->sdidata,
1068 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1075 dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1078 dmaengine_slave_config(host->dma, &conf);
1079 desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1085 desc->callback_param = host;
1087 dma_async_issue_pending(host->dma);
1092 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1099 struct s3cmci_host *host = mmc_priv(mmc);
1100 struct mmc_request *mrq = host->mrq;
1101 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1103 host->ccnt++;
1104 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1109 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1110 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1111 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1114 int res = s3cmci_setup_data(host, cmd->data);
1116 host->dcnt++;
1119 dbg(host, dbg_err, "setup data error %d\n", res);
1127 if (s3cmci_host_usedma(host))
1128 res = s3cmci_prepare_dma(host, cmd->data);
1130 res = s3cmci_prepare_pio(host, cmd->data);
1133 dbg(host, dbg_err, "data prepare error %d\n", res);
1143 s3cmci_send_command(host, cmd);
1146 s3cmci_enable_irq(host, true);
1151 struct s3cmci_host *host = mmc_priv(mmc);
1153 host->status = "mmc request";
1154 host->cmd_is_stop = 0;
1155 host->mrq = mrq;
1158 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1159 host->mrq->cmd->error = -ENOMEDIUM;
1165 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1171 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1173 if (host->real_rate <= ios->clock)
1180 host->prescaler = mci_psc;
1181 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1185 host->real_rate = 0;
1190 struct s3cmci_host *host = mmc_priv(mmc);
1195 mci_con = readl(host->base + S3C2410_SDICON);
1200 if (!host->is2440)
1206 if (host->is2440)
1211 if (host->pdata->set_power)
1212 host->pdata->set_power(ios->power_mode, ios->vdd);
1214 s3cmci_set_clk(host, ios);
1222 writel(mci_con, host->base + S3C2410_SDICON);
1226 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1227 host->real_rate/1000, ios->clock/1000);
1229 dbg(host, dbg_conf, "powered down.\n");
1232 host->bus_width = ios->bus_width;
1235 static void s3cmci_reset(struct s3cmci_host *host)
1237 u32 con = readl(host->base + S3C2410_SDICON);
1240 writel(con, host->base + S3C2410_SDICON);
1245 struct s3cmci_host *host = mmc_priv(mmc);
1251 con = readl(host->base + S3C2410_SDICON);
1252 host->sdio_irqen = enable;
1254 if (enable == host->sdio_irqen)
1259 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1261 if (!host->irq_state && !host->irq_disabled) {
1262 host->irq_state = true;
1263 enable_irq(host->irq);
1266 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1269 if (!host->irq_enabled && host->irq_state) {
1270 disable_irq_nosync(host->irq);
1271 host->irq_state = false;
1275 writel(con, host->base + S3C2410_SDICON);
1280 s3cmci_check_sdio_irq(host);
1296 struct s3cmci_host *host;
1301 host = container_of(nb, struct s3cmci_host, freq_transition);
1302 newclk = clk_get_rate(host->clk);
1303 mmc = host->mmc;
1305 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1306 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1309 host->clk_rate = newclk;
1313 s3cmci_set_clk(host, &mmc->ios);
1321 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1323 host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1325 return cpufreq_register_notifier(&host->freq_transition,
1329 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1331 cpufreq_unregister_notifier(&host->freq_transition,
1336 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1341 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1351 struct s3cmci_host *host = seq->private;
1353 seq_printf(seq, "Register base = 0x%p\n", host->base);
1354 seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1355 seq_printf(seq, "Prescale = %d\n", host->prescaler);
1356 seq_printf(seq, "is2440 = %d\n", host->is2440);
1357 seq_printf(seq, "IRQ = %d\n", host->irq);
1358 seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1359 seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1360 seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1361 seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1362 seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1363 seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1364 seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1399 struct s3cmci_host *host = seq->private;
1404 readl(host->base + rptr->addr));
1406 seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1413 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1415 struct device *dev = &host->pdev->dev;
1419 host->debug_root = root;
1421 debugfs_create_file("state", 0444, root, host, &s3cmci_state_fops);
1422 debugfs_create_file("regs", 0444, root, host, &s3cmci_regs_fops);
1425 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1427 debugfs_remove_recursive(host->debug_root);
1431 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1432 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1436 static int s3cmci_probe_pdata(struct s3cmci_host *host)
1438 struct platform_device *pdev = host->pdev;
1439 struct mmc_host *mmc = host->mmc;
1443 host->is2440 = platform_get_device_id(pdev)->driver_data;
1476 ret = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
1486 static int s3cmci_probe_dt(struct s3cmci_host *host)
1488 struct platform_device *pdev = host->pdev;
1490 struct mmc_host *mmc = host->mmc;
1493 host->is2440 = (long) of_device_get_match_data(&pdev->dev);
1510 struct s3cmci_host *host;
1520 host = mmc_priv(mmc);
1521 host->mmc = mmc;
1522 host->pdev = pdev;
1525 ret = s3cmci_probe_dt(host);
1527 ret = s3cmci_probe_pdata(host);
1532 host->pdata = pdev->dev.platform_data;
1534 spin_lock_init(&host->complete_lock);
1535 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1537 if (host->is2440) {
1538 host->sdiimsk = S3C2440_SDIIMSK;
1539 host->sdidata = S3C2440_SDIDATA;
1540 host->clk_div = 1;
1542 host->sdiimsk = S3C2410_SDIIMSK;
1543 host->sdidata = S3C2410_SDIDATA;
1544 host->clk_div = 2;
1547 host->complete_what = COMPLETION_NONE;
1548 host->pio_active = XFER_NONE;
1550 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1551 if (!host->mem) {
1559 host->mem = request_mem_region(host->mem->start,
1560 resource_size(host->mem), pdev->name);
1562 if (!host->mem) {
1568 host->base = ioremap(host->mem->start, resource_size(host->mem));
1569 if (!host->base) {
1575 host->irq = platform_get_irq(pdev, 0);
1576 if (host->irq <= 0) {
1581 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1591 disable_irq(host->irq);
1592 host->irq_state = false;
1596 if (s3cmci_host_usedma(host)) {
1597 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1598 ret = PTR_ERR_OR_ZERO(host->dma);
1605 host->clk = clk_get(&pdev->dev, "sdi");
1606 if (IS_ERR(host->clk)) {
1608 ret = PTR_ERR(host->clk);
1609 host->clk = NULL;
1613 ret = clk_prepare_enable(host->clk);
1619 host->clk_rate = clk_get_rate(host->clk);
1628 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1629 mmc->f_max = host->clk_rate / host->clk_div;
1631 if (host->pdata->ocr_avail)
1632 mmc->ocr_avail = host->pdata->ocr_avail;
1641 dbg(host, dbg_debug,
1643 (host->is2440?"2440":""),
1644 host->base, host->irq, host->irq_cd, host->dma);
1646 ret = s3cmci_cpufreq_register(host);
1654 dev_err(&pdev->dev, "failed to add mmc host.\n");
1658 s3cmci_debugfs_attach(host);
1662 s3cmci_host_usedma(host) ? "dma" : "pio",
1668 s3cmci_cpufreq_deregister(host);
1671 clk_disable_unprepare(host->clk);
1674 clk_put(host->clk);
1677 if (s3cmci_host_usedma(host))
1678 dma_release_channel(host->dma);
1681 free_irq(host->irq, host);
1684 iounmap(host->base);
1687 release_mem_region(host->mem->start, resource_size(host->mem));
1699 struct s3cmci_host *host = mmc_priv(mmc);
1701 if (host->irq_cd >= 0)
1702 free_irq(host->irq_cd, host);
1704 s3cmci_debugfs_remove(host);
1705 s3cmci_cpufreq_deregister(host);
1707 clk_disable_unprepare(host->clk);
1713 struct s3cmci_host *host = mmc_priv(mmc);
1717 clk_put(host->clk);
1719 tasklet_disable(&host->pio_tasklet);
1721 if (s3cmci_host_usedma(host))
1722 dma_release_channel(host->dma);
1724 free_irq(host->irq, host);
1726 iounmap(host->base);
1727 release_mem_region(host->mem->start, resource_size(host->mem));