Lines Matching refs:pcr
26 struct rtsx_pcr *pcr;
54 rtsx_pci_write_register(host->pcr, CARD_STOP,
71 rtsx_pci_read_register(host->pcr, start + i + j,
89 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
92 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
94 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
96 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
99 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
101 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
102 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
103 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
104 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
147 struct rtsx_pcr *pcr = host->pcr;
160 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
198 struct rtsx_pcr *pcr = host->pcr;
202 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
209 struct rtsx_pcr *pcr = host->pcr;
233 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
241 rtsx_pci_init_cmd(pcr);
242 sd_cmd_set_sd_cmd(pcr, cmd);
243 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
244 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
246 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
248 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
255 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
259 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
262 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
264 err = rtsx_pci_send_cmd(pcr, timeout);
279 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
320 rtsx_pci_write_register(pcr, SD_BUS_STAT,
327 struct rtsx_pcr *pcr = host->pcr;
342 rtsx_pci_init_cmd(pcr);
343 sd_cmd_set_sd_cmd(pcr, cmd);
344 sd_cmd_set_data_len(pcr, 1, byte_cnt);
345 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
349 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
352 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
354 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
357 err = rtsx_pci_send_cmd(pcr, timeout);
366 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
381 struct rtsx_pcr *pcr = host->pcr;
395 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
403 rtsx_pci_init_cmd(pcr);
404 sd_cmd_set_data_len(pcr, 1, byte_cnt);
405 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
408 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
410 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
413 err = rtsx_pci_send_cmd(pcr, timeout);
427 struct rtsx_pcr *pcr = host->pcr;
448 rtsx_pci_init_cmd(pcr);
449 sd_cmd_set_sd_cmd(pcr, cmd);
450 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
451 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
453 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
455 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
457 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
459 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
460 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
463 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
465 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
466 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
468 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
470 rtsx_pci_send_cmd_no_wait(pcr);
472 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
485 struct rtsx_pcr *pcr = host->pcr;
508 rtsx_pci_init_cmd(pcr);
509 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
510 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
512 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
514 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
516 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
518 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
519 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
522 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
524 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
525 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
527 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
529 rtsx_pci_send_cmd_no_wait(pcr);
530 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
541 rtsx_pci_write_register(host->pcr, SD_CFG1,
547 rtsx_pci_write_register(host->pcr, SD_CFG1,
615 struct rtsx_pcr *pcr = host->pcr;
620 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
623 rtsx_pci_write_register(pcr, SD_VPRX_CTL,
627 rtsx_pci_write_register(pcr, SD_VPTX_CTL,
630 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
631 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
633 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
634 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
689 rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
702 struct rtsx_pcr *pcr = host->pcr;
706 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
715 rtsx_pci_write_register(pcr, SD_CFG3,
720 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
797 struct rtsx_pcr *pcr = host->pcr;
812 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
818 mutex_lock(&pcr->pcr_mutex);
820 rtsx_pci_start_run(pcr);
822 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
824 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
825 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
855 mutex_unlock(&pcr->pcr_mutex);
896 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
904 struct rtsx_pcr *pcr = host->pcr;
911 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);
917 rtsx_pci_init_cmd(pcr);
918 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
919 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
921 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
923 err = rtsx_pci_send_cmd(pcr, 100);
927 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
931 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
937 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
942 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
951 struct rtsx_pcr *pcr = host->pcr;
956 rtsx_pci_init_cmd(pcr);
958 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
959 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
961 err = rtsx_pci_send_cmd(pcr, 100);
965 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
969 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
987 struct rtsx_pcr *pcr = host->pcr;
990 rtsx_pci_init_cmd(pcr);
995 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
998 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1000 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1002 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1007 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1010 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1012 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1014 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1015 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1017 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1028 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1030 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1031 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1033 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1038 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1040 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1042 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1044 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1045 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1047 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1052 err = rtsx_pci_send_cmd(pcr, 100);
1060 struct rtsx_pcr *pcr = host->pcr;
1065 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1068 mutex_lock(&pcr->pcr_mutex);
1070 rtsx_pci_start_run(pcr);
1099 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1102 mutex_unlock(&pcr->pcr_mutex);
1108 struct rtsx_pcr *pcr = host->pcr;
1115 mutex_lock(&pcr->pcr_mutex);
1117 rtsx_pci_start_run(pcr);
1120 val = rtsx_pci_readl(pcr, RTSX_BIPR);
1125 mutex_unlock(&pcr->pcr_mutex);
1133 struct rtsx_pcr *pcr = host->pcr;
1140 mutex_lock(&pcr->pcr_mutex);
1142 rtsx_pci_start_run(pcr);
1145 val = rtsx_pci_card_exist(pcr);
1150 mutex_unlock(&pcr->pcr_mutex);
1157 struct rtsx_pcr *pcr = host->pcr;
1171 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1180 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1190 struct rtsx_pcr *pcr = host->pcr;
1198 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1208 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1219 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1221 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1231 struct rtsx_pcr *pcr = host->pcr;
1241 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1245 mutex_lock(&pcr->pcr_mutex);
1247 rtsx_pci_start_run(pcr);
1260 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1272 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1275 mutex_unlock(&pcr->pcr_mutex);
1283 struct rtsx_pcr *pcr = host->pcr;
1289 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1293 mutex_lock(&pcr->pcr_mutex);
1295 rtsx_pci_start_run(pcr);
1300 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1304 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1308 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1323 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1326 mutex_unlock(&pcr->pcr_mutex);
1345 struct rtsx_pcr *pcr = host->pcr;
1347 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1349 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1351 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1353 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1355 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1357 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1359 if (pcr->extra_caps & EXTRA_CAPS_NO_MMC)
1399 struct rtsx_pcr *pcr;
1405 pcr = handle->pcr;
1406 if (!pcr)
1416 host->pcr = pcr;
1424 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1425 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1439 struct rtsx_pcr *pcr;
1445 pcr = host->pcr;
1446 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1447 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1458 rtsx_pci_complete_unfinished_transfer(pcr);