Lines Matching refs:host
2 * drivers/mmc/host/omap_hsmmc.c
34 #include <linux/mmc/host.h>
153 #define mmc_pdata(host) host->pdata
214 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
219 struct omap_hsmmc_host *host = mmc_priv(mmc);
229 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
235 host->vqmmc_enabled = 1;
251 struct omap_hsmmc_host *host = mmc_priv(mmc);
253 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
259 host->vqmmc_enabled = 0;
280 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
284 if (IS_ERR(host->pbias))
288 if (host->pbias_enabled == 0) {
289 ret = regulator_enable(host->pbias);
291 dev_err(host->dev, "pbias reg enable fail\n");
294 host->pbias_enabled = 1;
297 if (host->pbias_enabled == 1) {
298 ret = regulator_disable(host->pbias);
300 dev_err(host->dev, "pbias reg disable fail\n");
303 host->pbias_enabled = 0;
310 static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
312 struct mmc_host *mmc = host->mmc;
322 ret = omap_hsmmc_set_pbias(host, false);
344 ret = omap_hsmmc_set_pbias(host, true);
381 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
383 struct mmc_host *mmc = host->mmc;
393 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
399 dev_err(host->dev,
404 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
406 dev_err(host->dev,
414 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
417 struct mmc_host *mmc = host->mmc;
426 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
430 if ((ret != -ENODEV) && host->dev->of_node)
432 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
437 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
438 if (IS_ERR(host->pbias)) {
439 ret = PTR_ERR(host->pbias);
440 if ((ret != -ENODEV) && host->dev->of_node) {
441 dev_err(host->dev,
445 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
446 PTR_ERR(host->pbias));
450 if (mmc_pdata(host)->no_regulator_off_init)
453 ret = omap_hsmmc_disable_boot_regulators(host);
463 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
465 OMAP_HSMMC_WRITE(host->base, SYSCTL,
466 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
472 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
474 OMAP_HSMMC_WRITE(host->base, SYSCTL,
475 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
476 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
477 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
480 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
486 if (host->use_dma)
493 spin_lock_irqsave(&host->irq_lock, flags);
494 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
495 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
498 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
500 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
501 spin_unlock_irqrestore(&host->irq_lock, flags);
504 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
509 spin_lock_irqsave(&host->irq_lock, flags);
511 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
513 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
514 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
515 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
516 spin_unlock_irqrestore(&host->irq_lock, flags);
520 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
525 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
533 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
535 struct mmc_ios *ios = &host->mmc->ios;
540 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
542 omap_hsmmc_stop_clock(host);
544 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
546 clkdiv = calc_divisor(host, ios);
548 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
549 OMAP_HSMMC_WRITE(host->base, SYSCTL,
550 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
554 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
567 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
570 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
571 regval = OMAP_HSMMC_READ(host->base, HCTL);
572 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
577 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
580 omap_hsmmc_start_clock(host);
583 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
585 struct mmc_ios *ios = &host->mmc->ios;
588 con = OMAP_HSMMC_READ(host->base, CON);
596 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
599 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
600 OMAP_HSMMC_WRITE(host->base, HCTL,
601 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
604 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
605 OMAP_HSMMC_WRITE(host->base, HCTL,
606 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
611 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
613 struct mmc_ios *ios = &host->mmc->ios;
616 con = OMAP_HSMMC_READ(host->base, CON);
618 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
620 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
626 * Restore the MMC host context, if it was lost as result of a
629 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
631 struct mmc_ios *ios = &host->mmc->ios;
635 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
636 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
637 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
638 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
641 host->context_loss++;
643 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
644 if (host->power_mode != MMC_POWER_OFF &&
655 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
658 OMAP_HSMMC_WRITE(host->base, HCTL,
659 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
661 OMAP_HSMMC_WRITE(host->base, CAPA,
662 OMAP_HSMMC_READ(host->base, CAPA) | capa);
664 OMAP_HSMMC_WRITE(host->base, HCTL,
665 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
668 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
672 OMAP_HSMMC_WRITE(host->base, ISE, 0);
673 OMAP_HSMMC_WRITE(host->base, IE, 0);
674 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
677 if (host->power_mode == MMC_POWER_OFF)
680 omap_hsmmc_set_bus_width(host);
682 omap_hsmmc_set_clock(host);
684 omap_hsmmc_set_bus_mode(host);
687 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
688 host->context_loss);
693 * Save the MMC host context (store the number of power state changes so far).
695 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
697 host->con = OMAP_HSMMC_READ(host->base, CON);
698 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
699 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
700 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
705 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
710 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
720 static void send_init_stream(struct omap_hsmmc_host *host)
725 disable_irq(host->irq);
727 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
728 OMAP_HSMMC_WRITE(host->base, CON,
729 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
730 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
734 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
736 OMAP_HSMMC_WRITE(host->base, CON,
737 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
739 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
740 OMAP_HSMMC_READ(host->base, STAT);
742 enable_irq(host->irq);
750 struct omap_hsmmc_host *host = mmc_priv(mmc);
752 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
761 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
766 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
767 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
768 host->cmd = cmd;
770 omap_hsmmc_enable_irq(host, cmd);
772 host->response_busy = 0;
778 host->response_busy = 1;
788 if (cmd == host->mrq->stop)
793 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
794 host->mrq->sbc) {
796 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
806 if (host->use_dma)
809 host->req_in_progress = 1;
811 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
812 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
815 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
818 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
821 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
826 spin_lock_irqsave(&host->irq_lock, flags);
827 host->req_in_progress = 0;
828 dma_ch = host->dma_ch;
829 spin_unlock_irqrestore(&host->irq_lock, flags);
831 omap_hsmmc_disable_irq(host);
833 if (mrq->data && host->use_dma && dma_ch != -1)
835 host->mrq = NULL;
836 mmc_request_done(host->mmc, mrq);
843 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
846 struct mmc_request *mrq = host->mrq;
849 if (host->cmd && host->cmd->opcode == 6 &&
850 host->response_busy) {
851 host->response_busy = 0;
855 omap_hsmmc_request_done(host, mrq);
859 host->data = NULL;
866 if (data->stop && (data->error || !host->mrq->sbc))
867 omap_hsmmc_start_command(host, data->stop, NULL);
869 omap_hsmmc_request_done(host, data->mrq);
876 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
878 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
879 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
880 host->cmd = NULL;
881 omap_hsmmc_start_dma_transfer(host);
882 omap_hsmmc_start_command(host, host->mrq->cmd,
883 host->mrq->data);
887 host->cmd = NULL;
892 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
893 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
894 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
895 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
898 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
901 if ((host->data == NULL && !host->response_busy) || cmd->error)
902 omap_hsmmc_request_done(host, host->mrq);
908 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
913 host->data->error = errno;
915 spin_lock_irqsave(&host->irq_lock, flags);
916 dma_ch = host->dma_ch;
917 host->dma_ch = -1;
918 spin_unlock_irqrestore(&host->irq_lock, flags);
920 if (host->use_dma && dma_ch != -1) {
921 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
925 host->data->sg, host->data->sg_len,
926 mmc_get_dma_dir(host->data));
928 host->data->host_cookie = 0;
930 host->data = NULL;
937 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
959 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
962 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
975 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
981 OMAP_HSMMC_WRITE(host->base, SYSCTL,
982 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
988 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
989 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
995 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
999 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1000 dev_err(mmc_dev(host->mmc),
1005 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1009 omap_hsmmc_reset_controller_fsm(host, SRC);
1010 if (host->cmd)
1011 host->cmd->error = err;
1014 if (host->data) {
1015 omap_hsmmc_reset_controller_fsm(host, SRD);
1016 omap_hsmmc_dma_cleanup(host, err);
1017 } else if (host->mrq && host->mrq->cmd)
1018 host->mrq->cmd->error = err;
1021 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1027 data = host->data;
1028 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1031 omap_hsmmc_dbg_report_irq(host, status);
1035 if (host->data || host->response_busy) {
1037 host->response_busy = 0;
1040 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1043 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1047 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1048 if (!(ac12 & ACNE) && host->mrq->sbc) {
1054 host->mrq->sbc->error = error;
1055 hsmmc_command_incomplete(host, error, end_cmd);
1057 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1061 OMAP_HSMMC_WRITE(host->base, STAT, status);
1062 if (end_cmd || ((status & CC_EN) && host->cmd))
1063 omap_hsmmc_cmd_done(host, host->cmd);
1064 if ((end_trans || (status & TC_EN)) && host->mrq)
1065 omap_hsmmc_xfer_done(host, data);
1073 struct omap_hsmmc_host *host = dev_id;
1076 status = OMAP_HSMMC_READ(host->base, STAT);
1078 if (host->req_in_progress)
1079 omap_hsmmc_do_irq(host, status);
1082 mmc_signal_sdio_irq(host->mmc);
1085 status = OMAP_HSMMC_READ(host->base, STAT);
1091 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1095 OMAP_HSMMC_WRITE(host->base, HCTL,
1096 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1098 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1111 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1117 clk_disable_unprepare(host->dbclk);
1120 ret = omap_hsmmc_set_power(host, 0);
1124 ret = omap_hsmmc_set_power(host, 1);
1125 clk_prepare_enable(host->dbclk);
1130 OMAP_HSMMC_WRITE(host->base, HCTL,
1131 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1132 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1154 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1155 set_sd_bus_power(host);
1159 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1165 struct omap_hsmmc_host *host = param;
1170 spin_lock_irq(&host->irq_lock);
1171 if (host->dma_ch < 0) {
1172 spin_unlock_irq(&host->irq_lock);
1176 data = host->mrq->data;
1177 chan = omap_hsmmc_get_dma_chan(host, data);
1183 req_in_progress = host->req_in_progress;
1184 host->dma_ch = -1;
1185 spin_unlock_irq(&host->irq_lock);
1189 struct mmc_request *mrq = host->mrq;
1191 host->mrq = NULL;
1192 mmc_request_done(host->mmc, mrq);
1196 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1204 data->host_cookie != host->next_data.cookie) {
1205 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1206 " host->next_data.cookie %d\n",
1207 __func__, data->host_cookie, host->next_data.cookie);
1212 if (next || data->host_cookie != host->next_data.cookie) {
1217 dma_len = host->next_data.dma_len;
1218 host->next_data.dma_len = 0;
1229 host->dma_len = dma_len;
1237 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1245 .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1246 .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1267 BUG_ON(host->dma_ch != -1);
1269 chan = omap_hsmmc_get_dma_chan(host, data);
1275 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1283 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1289 tx->callback_param = host;
1294 host->dma_ch = 1;
1299 static void set_data_timeout(struct omap_hsmmc_host *host,
1307 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1312 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1334 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1337 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1339 struct mmc_request *req = host->mrq;
1344 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1346 set_data_timeout(host, req->data->timeout_ns,
1348 chan = omap_hsmmc_get_dma_chan(host, req->data);
1356 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1361 host->data = req->data;
1364 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1375 set_data_timeout(host, timeout, 0);
1380 if (host->use_dma) {
1381 ret = omap_hsmmc_setup_dma_transfer(host, req);
1383 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1393 struct omap_hsmmc_host *host = mmc_priv(mmc);
1396 if (host->use_dma && data->host_cookie) {
1397 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1407 struct omap_hsmmc_host *host = mmc_priv(mmc);
1414 if (host->use_dma) {
1415 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1417 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1418 &host->next_data, c))
1428 struct omap_hsmmc_host *host = mmc_priv(mmc);
1431 BUG_ON(host->req_in_progress);
1432 BUG_ON(host->dma_ch != -1);
1433 if (host->reqs_blocked)
1434 host->reqs_blocked = 0;
1435 WARN_ON(host->mrq != NULL);
1436 host->mrq = req;
1437 host->clk_rate = clk_get_rate(host->fclk);
1438 err = omap_hsmmc_prepare_data(host, req);
1443 host->mrq = NULL;
1447 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1448 omap_hsmmc_start_command(host, req->sbc, NULL);
1452 omap_hsmmc_start_dma_transfer(host);
1453 omap_hsmmc_start_command(host, req->cmd, req->data);
1459 struct omap_hsmmc_host *host = mmc_priv(mmc);
1462 if (ios->power_mode != host->power_mode) {
1465 omap_hsmmc_set_power(host, 0);
1468 omap_hsmmc_set_power(host, 1);
1474 host->power_mode = ios->power_mode;
1479 omap_hsmmc_set_bus_width(host);
1481 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1485 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1493 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1494 dev_dbg(mmc_dev(host->mmc),
1499 omap_hsmmc_set_clock(host);
1502 send_init_stream(host);
1504 omap_hsmmc_set_bus_mode(host);
1509 struct omap_hsmmc_host *host = mmc_priv(mmc);
1529 dev_info(host->dev, "found wl1251\n");
1544 struct omap_hsmmc_host *host = mmc_priv(mmc);
1548 spin_lock_irqsave(&host->irq_lock, flags);
1550 con = OMAP_HSMMC_READ(host->base, CON);
1551 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1553 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1557 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1561 OMAP_HSMMC_WRITE(host->base, CON, con);
1562 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1568 if (!host->req_in_progress || !enable)
1569 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1572 OMAP_HSMMC_READ(host->base, IE);
1574 spin_unlock_irqrestore(&host->irq_lock, flags);
1577 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1587 if (!host->dev->of_node || !host->wake_irq)
1590 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1592 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1600 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1601 struct pinctrl *p = devm_pinctrl_get(host->dev);
1608 dev_info(host->dev, "missing idle pinctrl state\n");
1616 OMAP_HSMMC_WRITE(host->base, HCTL,
1617 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1621 dev_pm_clear_wake_irq(host->dev);
1623 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1624 host->wake_irq = 0;
1628 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1633 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1641 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1642 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1644 value = OMAP_HSMMC_READ(host->base, CAPA);
1645 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1648 set_sd_bus_power(host);
1677 struct omap_hsmmc_host *host = mmc_priv(mmc);
1685 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1688 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1690 pm_runtime_get_sync(host->dev);
1693 OMAP_HSMMC_READ(host->base, CON));
1695 OMAP_HSMMC_READ(host->base, PSTATE));
1697 OMAP_HSMMC_READ(host->base, HCTL));
1699 OMAP_HSMMC_READ(host->base, SYSCTL));
1701 OMAP_HSMMC_READ(host->base, IE));
1703 OMAP_HSMMC_READ(host->base, ISE));
1705 OMAP_HSMMC_READ(host->base, CAPA));
1707 pm_runtime_mark_last_busy(host->dev);
1708 pm_runtime_put_autosuspend(host->dev);
1808 struct omap_hsmmc_host *host = NULL;
1855 host = mmc_priv(mmc);
1856 host->mmc = mmc;
1857 host->pdata = pdata;
1858 host->dev = &pdev->dev;
1859 host->use_dma = 1;
1860 host->dma_ch = -1;
1861 host->irq = irq;
1862 host->mapbase = res->start + pdata->reg_offset;
1863 host->base = base + pdata->reg_offset;
1864 host->power_mode = MMC_POWER_OFF;
1865 host->next_data.cookie = 1;
1866 host->pbias_enabled = 0;
1867 host->vqmmc_enabled = 0;
1869 platform_set_drvdata(pdev, host);
1872 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1883 spin_lock_init(&host->irq_lock);
1885 host->fclk = devm_clk_get(&pdev->dev, "fck");
1886 if (IS_ERR(host->fclk)) {
1887 ret = PTR_ERR(host->fclk);
1888 host->fclk = NULL;
1892 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1898 pm_runtime_enable(host->dev);
1899 pm_runtime_get_sync(host->dev);
1900 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1901 pm_runtime_use_autosuspend(host->dev);
1903 omap_hsmmc_context_save(host);
1905 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
1909 if (IS_ERR(host->dbclk)) {
1910 host->dbclk = NULL;
1911 } else if (clk_prepare_enable(host->dbclk) != 0) {
1912 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1913 host->dbclk = NULL;
1927 mmc->caps |= mmc_pdata(host)->caps;
1931 if (mmc_pdata(host)->nonremovable)
1934 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
1936 omap_hsmmc_conf_bus_power(host);
1938 host->rx_chan = dma_request_chan(&pdev->dev, "rx");
1939 if (IS_ERR(host->rx_chan)) {
1940 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
1941 ret = PTR_ERR(host->rx_chan);
1945 host->tx_chan = dma_request_chan(&pdev->dev, "tx");
1946 if (IS_ERR(host->tx_chan)) {
1947 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
1948 ret = PTR_ERR(host->tx_chan);
1960 dma_get_max_seg_size(host->rx_chan->device->dev),
1961 dma_get_max_seg_size(host->tx_chan->device->dev));
1964 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
1965 mmc_hostname(mmc), host);
1967 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1971 ret = omap_hsmmc_reg_get(host);
1976 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
1978 omap_hsmmc_disable_irq(host);
1988 ret = omap_hsmmc_configure_wake_irq(host);
1996 if (mmc_pdata(host)->name != NULL) {
2003 pm_runtime_mark_last_busy(host->dev);
2004 pm_runtime_put_autosuspend(host->dev);
2012 if (!IS_ERR_OR_NULL(host->tx_chan))
2013 dma_release_channel(host->tx_chan);
2014 if (!IS_ERR_OR_NULL(host->rx_chan))
2015 dma_release_channel(host->rx_chan);
2016 pm_runtime_dont_use_autosuspend(host->dev);
2017 pm_runtime_put_sync(host->dev);
2018 pm_runtime_disable(host->dev);
2019 clk_disable_unprepare(host->dbclk);
2028 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2030 pm_runtime_get_sync(host->dev);
2031 mmc_remove_host(host->mmc);
2033 dma_release_channel(host->tx_chan);
2034 dma_release_channel(host->rx_chan);
2036 dev_pm_clear_wake_irq(host->dev);
2037 pm_runtime_dont_use_autosuspend(host->dev);
2038 pm_runtime_put_sync(host->dev);
2039 pm_runtime_disable(host->dev);
2041 clk_disable_unprepare(host->dbclk);
2043 mmc_free_host(host->mmc);
2051 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2053 if (!host)
2056 pm_runtime_get_sync(host->dev);
2058 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2059 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2060 OMAP_HSMMC_WRITE(host->base, IE, 0);
2061 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2062 OMAP_HSMMC_WRITE(host->base, HCTL,
2063 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2066 clk_disable_unprepare(host->dbclk);
2068 pm_runtime_put_sync(host->dev);
2075 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2077 if (!host)
2080 pm_runtime_get_sync(host->dev);
2082 clk_prepare_enable(host->dbclk);
2084 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2085 omap_hsmmc_conf_bus_power(host);
2087 pm_runtime_mark_last_busy(host->dev);
2088 pm_runtime_put_autosuspend(host->dev);
2095 struct omap_hsmmc_host *host;
2099 host = dev_get_drvdata(dev);
2100 omap_hsmmc_context_save(host);
2103 spin_lock_irqsave(&host->irq_lock, flags);
2104 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2105 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2107 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2108 OMAP_HSMMC_WRITE(host->base, IE, 0);
2110 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2117 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2118 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2119 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2131 spin_unlock_irqrestore(&host->irq_lock, flags);
2137 struct omap_hsmmc_host *host;
2140 host = dev_get_drvdata(dev);
2141 omap_hsmmc_context_restore(host);
2144 spin_lock_irqsave(&host->irq_lock, flags);
2145 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2146 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2148 pinctrl_select_default_state(host->dev);
2151 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2152 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2153 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2155 pinctrl_select_default_state(host->dev);
2157 spin_unlock_irqrestore(&host->irq_lock, flags);