Lines Matching refs:ssp
49 struct mxs_ssp ssp;
65 struct mxs_ssp *ssp = &host->ssp;
76 !(readl(ssp->base + HW_SSP_STATUS(ssp)) &
87 struct mxs_ssp *ssp = &host->ssp;
91 ret = stmp_reset_block(ssp->base);
109 ssp->base + HW_SSP_TIMING(ssp));
116 writel(ctrl0, ssp->base + HW_SSP_CTRL0);
117 writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp));
129 struct mxs_ssp *ssp = &host->ssp;
133 cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
134 cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp));
135 cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp));
136 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp));
138 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
148 data->sg_len, ssp->dma_dir);
181 struct mxs_ssp *ssp = &host->ssp;
186 stat = readl(ssp->base + HW_SSP_CTRL1(ssp));
188 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
217 struct mxs_ssp *ssp = &host->ssp;
226 data->sg_len, ssp->dma_dir);
231 sgl = (struct scatterlist *) ssp->ssp_pio_words;
235 desc = dmaengine_prep_slave_sg(ssp->dmach,
236 sgl, sg_len, ssp->slave_dirn, flags);
243 data->sg_len, ssp->dma_dir);
251 struct mxs_ssp *ssp = &host->ssp;
265 ssp->ssp_pio_words[0] = ctrl0;
266 ssp->ssp_pio_words[1] = cmd0;
267 ssp->ssp_pio_words[2] = cmd1;
268 ssp->dma_dir = DMA_NONE;
269 ssp->slave_dirn = DMA_TRANS_NONE;
275 dma_async_issue_pending(ssp->dmach);
285 struct mxs_ssp *ssp = &host->ssp;
310 ssp->ssp_pio_words[0] = ctrl0;
311 ssp->ssp_pio_words[1] = cmd0;
312 ssp->ssp_pio_words[2] = cmd1;
313 ssp->dma_dir = DMA_NONE;
314 ssp->slave_dirn = DMA_TRANS_NONE;
320 dma_async_issue_pending(ssp->dmach);
358 struct mxs_ssp *ssp = &host->ssp;
402 if (ssp_is_old(ssp)) {
407 writel(data_size, ssp->base + HW_SSP_XFER_SIZE);
410 ssp->base + HW_SSP_BLOCK_SIZE);
424 timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns);
425 val = readl(ssp->base + HW_SSP_TIMING(ssp));
428 writel(val, ssp->base + HW_SSP_TIMING(ssp));
431 ssp->ssp_pio_words[0] = ctrl0;
432 ssp->ssp_pio_words[1] = cmd0;
433 ssp->ssp_pio_words[2] = cmd1;
434 ssp->dma_dir = DMA_NONE;
435 ssp->slave_dirn = DMA_TRANS_NONE;
443 ssp->dma_dir = dma_data_dir;
444 ssp->slave_dirn = slave_dirn;
450 dma_async_issue_pending(ssp->dmach);
507 mxs_ssp_set_clk_rate(&host->ssp, ios->clock);
513 struct mxs_ssp *ssp = &host->ssp;
522 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
524 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET);
527 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
529 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
534 if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) &
582 struct mxs_ssp *ssp;
593 ssp = &host->ssp;
594 ssp->dev = &pdev->dev;
595 ssp->base = devm_platform_ioremap_resource(pdev, 0);
596 if (IS_ERR(ssp->base)) {
597 ret = PTR_ERR(ssp->base);
601 ssp->devid = (enum mxs_ssp_id) of_id->data;
621 ssp->clk = devm_clk_get(&pdev->dev, NULL);
622 if (IS_ERR(ssp->clk)) {
623 ret = PTR_ERR(ssp->clk);
626 ret = clk_prepare_enable(ssp->clk);
636 ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
637 if (IS_ERR(ssp->dmach)) {
640 ret = PTR_ERR(ssp->dmach);
662 mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff;
663 mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff;
664 mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev);
684 dma_release_channel(ssp->dmach);
686 clk_disable_unprepare(ssp->clk);
696 struct mxs_ssp *ssp = &host->ssp;
700 if (ssp->dmach)
701 dma_release_channel(ssp->dmach);
703 clk_disable_unprepare(ssp->clk);
715 struct mxs_ssp *ssp = &host->ssp;
717 clk_disable_unprepare(ssp->clk);
725 struct mxs_ssp *ssp = &host->ssp;
727 return clk_prepare_enable(ssp->clk);