Lines Matching defs:host
30 #include <linux/mmc/host.h>
409 void __iomem *base; /* host base address */
410 void __iomem *top_base; /* host top register base address */
422 int irq; /* host interrupt */
609 static void msdc_reset_hw(struct msdc_host *host)
613 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
614 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
617 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
618 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
621 val = readl(host->base + MSDC_INT);
622 writel(val, host->base + MSDC_INT);
625 static void msdc_cmd_next(struct msdc_host *host,
627 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
645 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
676 if (host->dev_comp->support_64g) {
682 if (host->dev_comp->support_64g) {
700 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
701 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
704 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
705 if (host->dev_comp->support_64g)
706 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
708 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
711 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
717 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
722 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
730 dma_unmap_sg(host->dev, data->sg, data->sg_len,
736 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
738 struct mmc_host *mmc = mmc_from_priv(host);
752 if (host->dev_comp->clk_div_bits == 8)
753 sdr_get_field(host->base + MSDC_CFG,
756 sdr_get_field(host->base + MSDC_CFG,
766 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
770 host->timeout_ns = ns;
771 host->timeout_clks = clks;
773 timeout = msdc_timeout_cal(host, ns, clks);
774 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
778 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
782 timeout = msdc_timeout_cal(host, ns, clks);
783 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
787 static void msdc_gate_clock(struct msdc_host *host)
789 clk_disable_unprepare(host->src_clk_cg);
790 clk_disable_unprepare(host->src_clk);
791 clk_disable_unprepare(host->bus_clk);
792 clk_disable_unprepare(host->h_clk);
795 static void msdc_ungate_clock(struct msdc_host *host)
797 clk_prepare_enable(host->h_clk);
798 clk_prepare_enable(host->bus_clk);
799 clk_prepare_enable(host->src_clk);
800 clk_prepare_enable(host->src_clk_cg);
801 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
805 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
807 struct mmc_host *mmc = mmc_from_priv(host);
812 u32 tune_reg = host->dev_comp->pad_tune_reg;
815 dev_dbg(host->dev, "set mclk to 0\n");
816 host->mclk = 0;
818 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
822 flags = readl(host->base + MSDC_INTEN);
823 sdr_clr_bits(host->base + MSDC_INTEN, flags);
824 if (host->dev_comp->clk_div_bits == 8)
825 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
827 sdr_clr_bits(host->base + MSDC_CFG,
837 if (hz >= (host->src_clk_freq >> 2)) {
839 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
841 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
842 sclk = (host->src_clk_freq >> 2) / div;
847 hz >= (host->src_clk_freq >> 1)) {
848 if (host->dev_comp->clk_div_bits == 8)
849 sdr_set_bits(host->base + MSDC_CFG,
852 sdr_set_bits(host->base + MSDC_CFG,
854 sclk = host->src_clk_freq >> 1;
857 } else if (hz >= host->src_clk_freq) {
860 sclk = host->src_clk_freq;
863 if (hz >= (host->src_clk_freq >> 1)) {
865 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
867 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
868 sclk = (host->src_clk_freq >> 2) / div;
871 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
876 if (host->src_clk_cg)
877 clk_disable_unprepare(host->src_clk_cg);
879 clk_disable_unprepare(clk_get_parent(host->src_clk));
880 if (host->dev_comp->clk_div_bits == 8)
881 sdr_set_field(host->base + MSDC_CFG,
885 sdr_set_field(host->base + MSDC_CFG,
888 if (host->src_clk_cg)
889 clk_prepare_enable(host->src_clk_cg);
891 clk_prepare_enable(clk_get_parent(host->src_clk));
893 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
895 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
897 host->mclk = hz;
898 host->timing = timing;
900 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
901 sdr_set_bits(host->base + MSDC_INTEN, flags);
908 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
909 if (host->top_base) {
910 writel(host->def_tune_para.emmc_top_control,
911 host->top_base + EMMC_TOP_CONTROL);
912 writel(host->def_tune_para.emmc_top_cmd,
913 host->top_base + EMMC_TOP_CMD);
915 writel(host->def_tune_para.pad_tune,
916 host->base + tune_reg);
919 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
920 writel(host->saved_tune_para.pad_cmd_tune,
921 host->base + PAD_CMD_TUNE);
922 if (host->top_base) {
923 writel(host->saved_tune_para.emmc_top_control,
924 host->top_base + EMMC_TOP_CONTROL);
925 writel(host->saved_tune_para.emmc_top_cmd,
926 host->top_base + EMMC_TOP_CMD);
928 writel(host->saved_tune_para.pad_tune,
929 host->base + tune_reg);
934 host->dev_comp->hs400_tune)
935 sdr_set_field(host->base + tune_reg,
937 host->hs400_cmd_int_delay);
938 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
942 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
970 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
973 struct mmc_host *mmc = mmc_from_priv(host);
979 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
982 host->cmd_rsp = resp;
1013 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1015 if (host->timeout_ns != data->timeout_ns ||
1016 host->timeout_clks != data->timeout_clks)
1017 msdc_set_timeout(host, data->timeout_ns,
1020 writel(data->blocks, host->base + SDC_BLK_NUM);
1025 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
1030 WARN_ON(host->data);
1031 host->data = data;
1034 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1035 msdc_dma_setup(host, &host->dma, data);
1036 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1037 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1038 dev_dbg(host->dev, "DMA start\n");
1039 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1043 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1048 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1053 msdc_reset_hw(host);
1056 host->error |= REQ_STOP_EIO;
1059 host->error |= REQ_STOP_TMO;
1061 dev_err(host->dev,
1075 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1077 struct mmc_host *mmc = mmc_from_priv(host);
1081 reg_inten = readl(host->base + MSDC_INTEN);
1083 reg_int = readl(host->base + MSDC_INT);
1084 reg_ps = readl(host->base + MSDC_PS);
1087 __msdc_enable_sdio_irq(host, 0);
1094 static void msdc_track_cmd_data(struct msdc_host *host,
1097 if (host->error)
1098 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1099 __func__, cmd->opcode, cmd->arg, host->error);
1102 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1110 cancel_delayed_work(&host->req_timeout);
1112 spin_lock_irqsave(&host->lock, flags);
1113 host->mrq = NULL;
1114 spin_unlock_irqrestore(&host->lock, flags);
1116 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
1118 msdc_unprepare_data(host, mrq);
1119 if (host->error)
1120 msdc_reset_hw(host);
1121 mmc_request_done(mmc_from_priv(host), mrq);
1122 if (host->dev_comp->recheck_sdio_irq)
1123 msdc_recheck_sdio_irq(host);
1127 static bool msdc_cmd_done(struct msdc_host *host, int events,
1138 msdc_auto_cmd_done(host, events, mrq->sbc);
1147 spin_lock_irqsave(&host->lock, flags);
1148 done = !host->cmd;
1149 host->cmd = NULL;
1150 spin_unlock_irqrestore(&host->lock, flags);
1156 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1160 rsp[0] = readl(host->base + SDC_RESP3);
1161 rsp[1] = readl(host->base + SDC_RESP2);
1162 rsp[2] = readl(host->base + SDC_RESP1);
1163 rsp[3] = readl(host->base + SDC_RESP0);
1165 rsp[0] = readl(host->base + SDC_RESP0);
1178 msdc_reset_hw(host);
1181 host->error |= REQ_CMD_EIO;
1184 host->error |= REQ_CMD_TMO;
1188 dev_dbg(host->dev,
1193 msdc_cmd_next(host, mrq, cmd);
1198 * is correct before issue a request. but host design do below
1201 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1207 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
1210 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
1211 dev_err(host->dev, "CMD bus busy detected\n");
1212 host->error |= REQ_CMD_BUSY;
1213 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1220 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
1223 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
1224 dev_err(host->dev, "Controller busy detected\n");
1225 host->error |= REQ_CMD_BUSY;
1226 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1233 static void msdc_start_command(struct msdc_host *host,
1239 WARN_ON(host->cmd);
1240 host->cmd = cmd;
1242 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1243 if (!msdc_cmd_is_ready(host, mrq, cmd))
1246 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1247 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1248 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1249 msdc_reset_hw(host);
1253 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1255 spin_lock_irqsave(&host->lock, flags);
1256 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1257 spin_unlock_irqrestore(&host->lock, flags);
1259 writel(cmd->arg, host->base + SDC_ARG);
1260 writel(rawcmd, host->base + SDC_CMD);
1263 static void msdc_cmd_next(struct msdc_host *host,
1271 msdc_request_done(host, mrq);
1273 msdc_start_command(host, mrq, mrq->cmd);
1275 msdc_request_done(host, mrq);
1277 msdc_start_data(host, mrq, cmd, cmd->data);
1282 struct msdc_host *host = mmc_priv(mmc);
1284 host->error = 0;
1285 WARN_ON(host->mrq);
1286 host->mrq = mrq;
1289 msdc_prepare_data(host, mrq);
1297 msdc_start_command(host, mrq, mrq->sbc);
1299 msdc_start_command(host, mrq, mrq->cmd);
1304 struct msdc_host *host = mmc_priv(mmc);
1310 msdc_prepare_data(host, mrq);
1317 struct msdc_host *host = mmc_priv(mmc);
1325 msdc_unprepare_data(host, mrq);
1329 static void msdc_data_xfer_next(struct msdc_host *host,
1334 msdc_start_command(host, mrq, mrq->stop);
1336 msdc_request_done(host, mrq);
1339 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
1350 spin_lock_irqsave(&host->lock, flags);
1351 done = !host->data;
1353 host->data = NULL;
1354 spin_unlock_irqrestore(&host->lock, flags);
1361 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1362 readl(host->base + MSDC_DMA_CFG));
1363 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1365 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1367 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1368 dev_dbg(host->dev, "DMA stop\n");
1373 dev_dbg(host->dev, "interrupt events: %x\n", events);
1374 msdc_reset_hw(host);
1375 host->error |= REQ_DAT_ERR;
1383 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1385 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1389 msdc_data_xfer_next(host, mrq, data);
1395 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1397 u32 val = readl(host->base + SDC_CFG);
1414 writel(val, host->base + SDC_CFG);
1415 dev_dbg(host->dev, "Bus Width = %d", width);
1420 struct msdc_host *host = mmc_priv(mmc);
1426 dev_err(host->dev, "Unsupported signal voltage!\n");
1432 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1439 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1441 pinctrl_select_state(host->pinctrl, host->pins_default);
1448 struct msdc_host *host = mmc_priv(mmc);
1449 u32 status = readl(host->base + MSDC_PS);
1457 struct msdc_host *host = container_of(work, struct msdc_host,
1461 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1462 if (host->mrq) {
1463 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1464 host->mrq, host->mrq->cmd->opcode);
1465 if (host->cmd) {
1466 dev_err(host->dev, "%s: aborting cmd=%d\n",
1467 __func__, host->cmd->opcode);
1468 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1469 host->cmd);
1470 } else if (host->data) {
1471 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1472 __func__, host->mrq->cmd->opcode,
1473 host->data->blocks);
1474 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1475 host->data);
1480 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1483 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1484 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1485 if (host->dev_comp->recheck_sdio_irq)
1486 msdc_recheck_sdio_irq(host);
1488 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1489 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1496 struct msdc_host *host = mmc_priv(mmc);
1498 spin_lock_irqsave(&host->lock, flags);
1499 __msdc_enable_sdio_irq(host, enb);
1500 spin_unlock_irqrestore(&host->lock, flags);
1503 pm_runtime_get_noresume(host->dev);
1505 pm_runtime_put_noidle(host->dev);
1508 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1510 struct mmc_host *mmc = mmc_from_priv(host);
1515 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1518 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1523 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1526 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1530 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
1539 struct msdc_host *host = (struct msdc_host *) dev_id;
1540 struct mmc_host *mmc = mmc_from_priv(host);
1549 spin_lock_irqsave(&host->lock, flags);
1550 events = readl(host->base + MSDC_INT);
1551 event_mask = readl(host->base + MSDC_INTEN);
1553 __msdc_enable_sdio_irq(host, 0);
1555 writel(events & event_mask, host->base + MSDC_INT);
1557 mrq = host->mrq;
1558 cmd = host->cmd;
1559 data = host->data;
1560 spin_unlock_irqrestore(&host->lock, flags);
1566 if (host->internal_cd)
1576 msdc_cmdq_irq(host, events);
1578 writel(events, host->base + MSDC_INT);
1583 dev_err(host->dev,
1590 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1593 msdc_cmd_done(host, events, mrq, cmd);
1595 msdc_data_xfer_done(host, events, mrq, data);
1601 static void msdc_init_hw(struct msdc_host *host)
1604 u32 tune_reg = host->dev_comp->pad_tune_reg;
1606 if (host->reset) {
1607 reset_control_assert(host->reset);
1609 reset_control_deassert(host->reset);
1613 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1616 msdc_reset_hw(host);
1619 writel(0, host->base + MSDC_INTEN);
1620 val = readl(host->base + MSDC_INT);
1621 writel(val, host->base + MSDC_INT);
1624 if (host->internal_cd) {
1625 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1627 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1628 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1629 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1631 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1632 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1633 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1636 if (host->top_base) {
1637 writel(0, host->top_base + EMMC_TOP_CONTROL);
1638 writel(0, host->top_base + EMMC_TOP_CMD);
1640 writel(0, host->base + tune_reg);
1642 writel(0, host->base + MSDC_IOCON);
1643 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1644 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1645 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1646 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1647 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1649 if (host->dev_comp->stop_clk_fix) {
1650 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1652 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1654 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1658 if (host->dev_comp->busy_check)
1659 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
1661 if (host->dev_comp->async_fifo) {
1662 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1664 if (host->dev_comp->enhance_rx) {
1665 if (host->top_base)
1666 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1669 sdr_set_bits(host->base + SDC_ADV_CFG0,
1672 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1674 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1678 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1680 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1684 if (host->dev_comp->support_64g)
1685 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1687 if (host->dev_comp->data_tune) {
1688 if (host->top_base) {
1689 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1691 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1693 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1696 sdr_set_bits(host->base + tune_reg,
1702 if (host->top_base)
1703 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1706 sdr_set_bits(host->base + tune_reg,
1713 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1716 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1717 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1720 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1722 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1723 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1724 if (host->top_base) {
1725 host->def_tune_para.emmc_top_control =
1726 readl(host->top_base + EMMC_TOP_CONTROL);
1727 host->def_tune_para.emmc_top_cmd =
1728 readl(host->top_base + EMMC_TOP_CMD);
1729 host->saved_tune_para.emmc_top_control =
1730 readl(host->top_base + EMMC_TOP_CONTROL);
1731 host->saved_tune_para.emmc_top_cmd =
1732 readl(host->top_base + EMMC_TOP_CMD);
1734 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1735 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1737 dev_dbg(host->dev, "init hardware done!");
1740 static void msdc_deinit_hw(struct msdc_host *host)
1744 if (host->internal_cd) {
1746 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1747 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1751 writel(0, host->base + MSDC_INTEN);
1753 val = readl(host->base + MSDC_INT);
1754 writel(val, host->base + MSDC_INT);
1758 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1773 if (host->dev_comp->support_64g)
1778 if (host->dev_comp->support_64g)
1785 if (host->dev_comp->support_64g)
1792 struct msdc_host *host = mmc_priv(mmc);
1795 msdc_set_buswidth(host, ios->bus_width);
1801 msdc_init_hw(host);
1805 dev_err(host->dev, "Failed to set vmmc power!\n");
1811 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1814 dev_err(host->dev, "Failed to set vqmmc power!\n");
1816 host->vqmmc_enabled = true;
1823 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1825 host->vqmmc_enabled = false;
1832 if (host->mclk != ios->clock || host->timing != ios->timing)
1833 msdc_set_mclk(host, ios->timing, ios->clock);
1853 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1861 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1882 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1891 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1893 u32 tune_reg = host->dev_comp->pad_tune_reg;
1895 if (host->top_base)
1896 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1899 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1903 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1905 u32 tune_reg = host->dev_comp->pad_tune_reg;
1907 if (host->top_base)
1908 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
1911 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
1917 struct msdc_host *host = mmc_priv(mmc);
1923 u32 tune_reg = host->dev_comp->pad_tune_reg;
1929 sdr_set_field(host->base + tune_reg,
1931 host->hs200_cmd_int_delay);
1933 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1935 msdc_set_cmd_delay(host, i);
1951 final_rise_delay = get_best_delay(host, rise_delay);
1957 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1959 msdc_set_cmd_delay(host, i);
1975 final_fall_delay = get_best_delay(host, fall_delay);
1982 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1985 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1988 msdc_set_cmd_delay(host, final_delay);
1990 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1994 sdr_set_field(host->base + tune_reg,
2000 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2001 internal_delay_phase = get_best_delay(host, internal_delay);
2002 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2005 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2011 struct msdc_host *host = mmc_priv(mmc);
2019 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2020 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2024 sdr_set_field(host->base + MSDC_PAD_TUNE,
2026 host->hs200_cmd_int_delay);
2028 if (host->hs400_cmd_resp_sel_rising)
2029 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2031 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2033 sdr_set_field(host->base + PAD_CMD_TUNE,
2050 final_cmd_delay = get_best_delay(host, cmd_delay);
2051 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2055 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2061 struct msdc_host *host = mmc_priv(mmc);
2067 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2068 host->latch_ck);
2069 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2070 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2072 msdc_set_data_delay(host, i);
2077 final_rise_delay = get_best_delay(host, rise_delay);
2083 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2084 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2086 msdc_set_data_delay(host, i);
2091 final_fall_delay = get_best_delay(host, fall_delay);
2096 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2097 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2100 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2101 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2104 msdc_set_data_delay(host, final_delay);
2106 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2116 struct msdc_host *host = mmc_priv(mmc);
2122 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2123 host->latch_ck);
2125 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2126 sdr_clr_bits(host->base + MSDC_IOCON,
2129 msdc_set_cmd_delay(host, i);
2130 msdc_set_data_delay(host, i);
2135 final_rise_delay = get_best_delay(host, rise_delay);
2141 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2142 sdr_set_bits(host->base + MSDC_IOCON,
2145 msdc_set_cmd_delay(host, i);
2146 msdc_set_data_delay(host, i);
2151 final_fall_delay = get_best_delay(host, fall_delay);
2156 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2157 sdr_clr_bits(host->base + MSDC_IOCON,
2161 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2162 sdr_set_bits(host->base + MSDC_IOCON,
2167 msdc_set_cmd_delay(host, final_delay);
2168 msdc_set_data_delay(host, final_delay);
2170 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2176 struct msdc_host *host = mmc_priv(mmc);
2178 u32 tune_reg = host->dev_comp->pad_tune_reg;
2180 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2182 if (host->hs400_mode) {
2183 sdr_clr_bits(host->base + MSDC_IOCON,
2185 msdc_set_data_delay(host, 0);
2189 if (host->hs400_mode &&
2190 host->dev_comp->hs400_tune)
2195 dev_err(host->dev, "Tune response fail!\n");
2198 if (host->hs400_mode == false) {
2201 dev_err(host->dev, "Tune data fail!\n");
2205 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2206 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2207 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2208 if (host->top_base) {
2209 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2211 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2219 struct msdc_host *host = mmc_priv(mmc);
2220 host->hs400_mode = true;
2222 if (host->top_base)
2223 writel(host->hs400_ds_delay,
2224 host->top_base + EMMC50_PAD_DS_TUNE);
2226 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2228 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2230 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2237 struct msdc_host *host = mmc_priv(mmc);
2239 sdr_set_bits(host->base + EMMC_IOCON, 1);
2241 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2247 struct msdc_host *host = mmc_priv(mmc);
2249 spin_lock_irqsave(&host->lock, flags);
2250 __msdc_enable_sdio_irq(host, 1);
2251 spin_unlock_irqrestore(&host->lock, flags);
2256 struct msdc_host *host = mmc_priv(mmc);
2262 if (!host->internal_cd)
2265 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2274 struct msdc_host *host = mmc_priv(mmc);
2277 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2279 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2281 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2283 msdc_set_timeout(host, 1000000000ULL, 0);
2288 struct msdc_host *host = mmc_priv(mmc);
2292 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2294 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2296 val = readl(host->base + MSDC_INT);
2297 writel(val, host->base + MSDC_INT);
2300 sdr_set_field(host->base + MSDC_DMA_CTRL,
2302 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2305 msdc_reset_hw(host);
2353 struct msdc_host *host)
2356 &host->latch_ck);
2359 &host->hs400_ds_delay);
2362 &host->hs200_cmd_int_delay);
2365 &host->hs400_cmd_int_delay);
2369 host->hs400_cmd_resp_sel_rising = true;
2371 host->hs400_cmd_resp_sel_rising = false;
2375 host->cqhci = true;
2377 host->cqhci = false;
2383 struct msdc_host *host;
2392 /* Allocate MMC host for this device */
2397 host = mmc_priv(mmc);
2402 host->base = devm_platform_ioremap_resource(pdev, 0);
2403 if (IS_ERR(host->base)) {
2404 ret = PTR_ERR(host->base);
2410 host->top_base = devm_ioremap_resource(&pdev->dev, res);
2411 if (IS_ERR(host->top_base))
2412 host->top_base = NULL;
2419 host->src_clk = devm_clk_get(&pdev->dev, "source");
2420 if (IS_ERR(host->src_clk)) {
2421 ret = PTR_ERR(host->src_clk);
2425 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2426 if (IS_ERR(host->h_clk)) {
2427 ret = PTR_ERR(host->h_clk);
2431 host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
2432 if (IS_ERR(host->bus_clk))
2433 host->bus_clk = NULL;
2435 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
2436 if (IS_ERR(host->src_clk_cg))
2437 host->src_clk_cg = NULL;
2439 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2441 if (IS_ERR(host->reset))
2442 return PTR_ERR(host->reset);
2444 host->irq = platform_get_irq(pdev, 0);
2445 if (host->irq < 0) {
2446 ret = host->irq;
2450 host->pinctrl = devm_pinctrl_get(&pdev->dev);
2451 if (IS_ERR(host->pinctrl)) {
2452 ret = PTR_ERR(host->pinctrl);
2457 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2458 if (IS_ERR(host->pins_default)) {
2459 ret = PTR_ERR(host->pins_default);
2464 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2465 if (IS_ERR(host->pins_uhs)) {
2466 ret = PTR_ERR(host->pins_uhs);
2471 msdc_of_property_parse(pdev, host);
2473 host->dev = &pdev->dev;
2474 host->dev_comp = of_device_get_match_data(&pdev->dev);
2475 host->src_clk_freq = clk_get_rate(host->src_clk);
2476 /* Set host parameters to mmc */
2478 if (host->dev_comp->clk_div_bits == 8)
2479 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2481 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2485 host->dev_comp->use_internal_cd) {
2490 host->internal_cd = true;
2497 if (host->cqhci)
2501 if (host->dev_comp->support_64g)
2508 if (host->dev_comp->support_64g)
2509 host->dma_mask = DMA_BIT_MASK(36);
2511 host->dma_mask = DMA_BIT_MASK(32);
2512 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2514 host->timeout_clks = 3 * 1048576;
2515 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2517 &host->dma.gpd_addr, GFP_KERNEL);
2518 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2520 &host->dma.bd_addr, GFP_KERNEL);
2521 if (!host->dma.gpd || !host->dma.bd) {
2525 msdc_init_gpd_bd(host, &host->dma);
2526 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2527 spin_lock_init(&host->lock);
2530 msdc_ungate_clock(host);
2531 msdc_init_hw(host);
2534 host->cq_host = devm_kzalloc(mmc->parent,
2535 sizeof(*host->cq_host),
2537 if (!host->cq_host) {
2541 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2542 host->cq_host->mmio = host->base + 0x800;
2543 host->cq_host->ops = &msdc_cmdq_ops;
2544 ret = cqhci_init(host->cq_host, mmc, true);
2553 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2554 IRQF_TRIGGER_NONE, pdev->name, host);
2558 pm_runtime_set_active(host->dev);
2559 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2560 pm_runtime_use_autosuspend(host->dev);
2561 pm_runtime_enable(host->dev);
2569 pm_runtime_disable(host->dev);
2572 msdc_deinit_hw(host);
2573 msdc_gate_clock(host);
2575 if (host->dma.gpd)
2578 host->dma.gpd, host->dma.gpd_addr);
2579 if (host->dma.bd)
2582 host->dma.bd, host->dma.bd_addr);
2592 struct msdc_host *host;
2595 host = mmc_priv(mmc);
2597 pm_runtime_get_sync(host->dev);
2601 msdc_deinit_hw(host);
2602 msdc_gate_clock(host);
2604 pm_runtime_disable(host->dev);
2605 pm_runtime_put_noidle(host->dev);
2608 host->dma.gpd, host->dma.gpd_addr);
2610 host->dma.bd, host->dma.bd_addr);
2617 static void msdc_save_reg(struct msdc_host *host)
2619 u32 tune_reg = host->dev_comp->pad_tune_reg;
2621 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2622 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2623 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2624 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2625 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2626 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2627 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2628 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2629 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2630 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2631 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2632 if (host->top_base) {
2633 host->save_para.emmc_top_control =
2634 readl(host->top_base + EMMC_TOP_CONTROL);
2635 host->save_para.emmc_top_cmd =
2636 readl(host->top_base + EMMC_TOP_CMD);
2637 host->save_para.emmc50_pad_ds_tune =
2638 readl(host->top_base + EMMC50_PAD_DS_TUNE);
2640 host->save_para.pad_tune = readl(host->base + tune_reg);
2644 static void msdc_restore_reg(struct msdc_host *host)
2646 struct mmc_host *mmc = mmc_from_priv(host);
2647 u32 tune_reg = host->dev_comp->pad_tune_reg;
2649 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2650 writel(host->save_para.iocon, host->base + MSDC_IOCON);
2651 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2652 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2653 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2654 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2655 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2656 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2657 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2658 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2659 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2660 if (host->top_base) {
2661 writel(host->save_para.emmc_top_control,
2662 host->top_base + EMMC_TOP_CONTROL);
2663 writel(host->save_para.emmc_top_cmd,
2664 host->top_base + EMMC_TOP_CMD);
2665 writel(host->save_para.emmc50_pad_ds_tune,
2666 host->top_base + EMMC50_PAD_DS_TUNE);
2668 writel(host->save_para.pad_tune, host->base + tune_reg);
2672 __msdc_enable_sdio_irq(host, 1);
2678 struct msdc_host *host = mmc_priv(mmc);
2680 msdc_save_reg(host);
2681 msdc_gate_clock(host);
2688 struct msdc_host *host = mmc_priv(mmc);
2690 msdc_ungate_clock(host);
2691 msdc_restore_reg(host);