Lines Matching defs:data
406 struct mmc_data *data;
415 u32 timeout_ns; /* data timeout ns */
416 u32 timeout_clks; /* data timeout clks */
564 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
565 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
566 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
567 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
568 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
569 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
570 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
571 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
572 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
646 struct mmc_data *data)
655 sg = data->sg;
668 for_each_sg(data->sg, sg, data->sg_count, j) {
690 if (j == data->sg_count - 1) /* the last bd */
713 struct mmc_data *data = mrq->data;
715 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
716 data->host_cookie |= MSDC_PREPARE_FLAG;
717 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
718 mmc_get_dma_dir(data));
724 struct mmc_data *data = mrq->data;
726 if (data->host_cookie & MSDC_ASYNC_FLAG)
729 if (data->host_cookie & MSDC_PREPARE_FLAG) {
730 dma_unmap_sg(host->dev, data->sg, data->sg_len,
731 mmc_get_dma_dir(data));
732 data->host_cookie &= ~MSDC_PREPARE_FLAG;
758 /*DDR mode will double the clk cycles for data timeout */
996 if (cmd->data) {
997 struct mmc_data *data = cmd->data;
1005 rawcmd |= ((data->blksz & 0xFFF) << 16);
1006 if (data->flags & MMC_DATA_WRITE)
1008 if (data->blocks > 1)
1015 if (host->timeout_ns != data->timeout_ns ||
1016 host->timeout_clks != data->timeout_clks)
1017 msdc_set_timeout(host, data->timeout_ns,
1018 data->timeout_clks);
1020 writel(data->blocks, host->base + SDC_BLK_NUM);
1026 struct mmc_command *cmd, struct mmc_data *data)
1030 WARN_ON(host->data);
1031 host->data = data;
1032 read = data->flags & MMC_DATA_READ;
1035 msdc_dma_setup(host, &host->dma, data);
1039 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1040 __func__, cmd->opcode, data->blocks, read);
1095 struct mmc_command *cmd, struct mmc_data *data)
1116 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
1117 if (mrq->data)
1174 * should not clear fifo/interrupt as the tune data
1217 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1219 /* R1B or with data, should check SDCBUSY */
1274 else if (!cmd->data)
1277 msdc_start_data(host, mrq, cmd, cmd->data);
1288 if (mrq->data)
1305 struct mmc_data *data = mrq->data;
1307 if (!data)
1311 data->host_cookie |= MSDC_ASYNC_FLAG;
1318 struct mmc_data *data;
1320 data = mrq->data;
1321 if (!data)
1323 if (data->host_cookie) {
1324 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1330 struct mmc_request *mrq, struct mmc_data *data)
1340 struct mmc_request *mrq, struct mmc_data *data)
1351 done = !host->data;
1353 host->data = NULL;
1358 stop = data->stop;
1371 data->bytes_xfered = data->blocks * data->blksz;
1376 data->bytes_xfered = 0;
1379 data->error = -ETIMEDOUT;
1381 data->error = -EILSEQ;
1384 __func__, mrq->cmd->opcode, data->blocks);
1386 (int)data->error, data->bytes_xfered);
1389 msdc_data_xfer_next(host, mrq, data);
1461 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1470 } else if (host->data) {
1471 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1473 host->data->blocks);
1475 host->data);
1546 struct mmc_data *data;
1559 data = host->data;
1594 else if (data)
1595 msdc_data_xfer_done(host, events, mrq, data);
1719 /* Configure to default data timeout */
2106 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2111 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2201 dev_err(host->dev, "Tune data fail!\n");
2280 /* default write data / busy timeout 20s */
2282 /* default read data timeout 1s */