Lines Matching defs:base
409 void __iomem *base; /* host base address */
410 void __iomem *top_base; /* host top register base address */
613 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
614 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
617 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
618 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
621 val = readl(host->base + MSDC_INT);
622 writel(val, host->base + MSDC_INT);
700 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
701 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
704 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
706 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
708 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
753 sdr_get_field(host->base + MSDC_CFG,
756 sdr_get_field(host->base + MSDC_CFG,
774 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
783 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
801 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
818 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
822 flags = readl(host->base + MSDC_INTEN);
823 sdr_clr_bits(host->base + MSDC_INTEN, flags);
825 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
827 sdr_clr_bits(host->base + MSDC_CFG,
849 sdr_set_bits(host->base + MSDC_CFG,
852 sdr_set_bits(host->base + MSDC_CFG,
871 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
881 sdr_set_field(host->base + MSDC_CFG,
885 sdr_set_field(host->base + MSDC_CFG,
893 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
895 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
901 sdr_set_bits(host->base + MSDC_INTEN, flags);
908 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
916 host->base + tune_reg);
919 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
921 host->base + PAD_CMD_TUNE);
929 host->base + tune_reg);
935 sdr_set_field(host->base + tune_reg,
1013 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1020 writel(data->blocks, host->base + SDC_BLK_NUM);
1036 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1037 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1048 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1081 reg_inten = readl(host->base + MSDC_INTEN);
1083 reg_int = readl(host->base + MSDC_INT);
1084 reg_ps = readl(host->base + MSDC_PS);
1156 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1160 rsp[0] = readl(host->base + SDC_RESP3);
1161 rsp[1] = readl(host->base + SDC_RESP2);
1162 rsp[2] = readl(host->base + SDC_RESP1);
1163 rsp[3] = readl(host->base + SDC_RESP0);
1165 rsp[0] = readl(host->base + SDC_RESP0);
1207 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
1210 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
1220 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
1223 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
1246 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1247 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1256 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1259 writel(cmd->arg, host->base + SDC_ARG);
1260 writel(rawcmd, host->base + SDC_CMD);
1362 readl(host->base + MSDC_DMA_CFG));
1363 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1365 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1367 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1397 u32 val = readl(host->base + SDC_CFG);
1414 writel(val, host->base + SDC_CFG);
1449 u32 status = readl(host->base + MSDC_PS);
1483 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1484 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1488 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1489 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1550 events = readl(host->base + MSDC_INT);
1551 event_mask = readl(host->base + MSDC_INTEN);
1555 writel(events & event_mask, host->base + MSDC_INT);
1578 writel(events, host->base + MSDC_INT);
1613 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1619 writel(0, host->base + MSDC_INTEN);
1620 val = readl(host->base + MSDC_INT);
1621 writel(val, host->base + MSDC_INT);
1625 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1627 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1628 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1629 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1631 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1632 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1633 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1640 writel(0, host->base + tune_reg);
1642 writel(0, host->base + MSDC_IOCON);
1643 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1644 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1645 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1646 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1647 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1650 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1652 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1654 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1659 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
1662 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1669 sdr_set_bits(host->base + SDC_ADV_CFG0,
1672 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1674 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1678 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1680 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1685 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1696 sdr_set_bits(host->base + tune_reg,
1706 sdr_set_bits(host->base + tune_reg,
1713 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1716 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1717 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1720 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1722 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1723 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1734 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1735 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1746 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1747 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1751 writel(0, host->base + MSDC_INTEN);
1753 val = readl(host->base + MSDC_INT);
1754 writel(val, host->base + MSDC_INT);
1899 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1911 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
1929 sdr_set_field(host->base + tune_reg,
1933 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1957 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1982 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1985 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1994 sdr_set_field(host->base + tune_reg,
2002 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2019 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2020 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2024 sdr_set_field(host->base + MSDC_PAD_TUNE,
2029 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2031 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2033 sdr_set_field(host->base + PAD_CMD_TUNE,
2051 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2067 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2069 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2070 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2083 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2084 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2096 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2097 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2100 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2101 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2122 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2125 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2126 sdr_clr_bits(host->base + MSDC_IOCON,
2141 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2142 sdr_set_bits(host->base + MSDC_IOCON,
2156 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2157 sdr_clr_bits(host->base + MSDC_IOCON,
2161 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2162 sdr_set_bits(host->base + MSDC_IOCON,
2183 sdr_clr_bits(host->base + MSDC_IOCON,
2205 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2206 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2207 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2226 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2228 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2230 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2239 sdr_set_bits(host->base + EMMC_IOCON, 1);
2241 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2265 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2277 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2279 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2292 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2294 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2296 val = readl(host->base + MSDC_INT);
2297 writel(val, host->base + MSDC_INT);
2300 sdr_set_field(host->base + MSDC_DMA_CTRL,
2302 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2402 host->base = devm_platform_ioremap_resource(pdev, 0);
2403 if (IS_ERR(host->base)) {
2404 ret = PTR_ERR(host->base);
2542 host->cq_host->mmio = host->base + 0x800;
2621 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2622 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2623 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2624 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2625 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2626 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2627 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2628 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2629 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2630 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2631 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2640 host->save_para.pad_tune = readl(host->base + tune_reg);
2649 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2650 writel(host->save_para.iocon, host->base + MSDC_IOCON);
2651 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2652 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2653 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2654 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2655 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2656 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2657 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2658 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2659 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2668 writel(host->save_para.pad_tune, host->base + tune_reg);
2705 val = readl(((struct msdc_host *)mmc_priv(mmc))->base + MSDC_INT);
2706 writel(val, ((struct msdc_host *)mmc_priv(mmc))->base + MSDC_INT);