Lines Matching defs:EMMC_TOP_CONTROL
88 #define EMMC_TOP_CONTROL 0x00
273 /* EMMC_TOP_CONTROL mask */
911 host->top_base + EMMC_TOP_CONTROL);
924 host->top_base + EMMC_TOP_CONTROL);
1637 writel(0, host->top_base + EMMC_TOP_CONTROL);
1666 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1689 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1691 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1703 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1726 readl(host->top_base + EMMC_TOP_CONTROL);
1730 readl(host->top_base + EMMC_TOP_CONTROL);
1908 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2210 EMMC_TOP_CONTROL);
2634 readl(host->top_base + EMMC_TOP_CONTROL);
2662 host->top_base + EMMC_TOP_CONTROL);