Lines Matching refs:base
49 void __iomem *base;
159 host->base + MMCI_STM32_IDMABASE0R);
161 host->base + MMCI_STM32_IDMACTRLR);
177 writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
178 writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
179 writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
180 writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
182 host->base + MMCI_STM32_IDMACTRLR);
189 writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
259 if (!dlyb || !dlyb->base)
263 writel_relaxed(0, dlyb->base + DLYB_CR);
296 host->base + MMCIMASK0);
332 void __iomem *base = host->base;
335 mask = readl_relaxed(base + MMCIMASK0);
336 sdmmc_status = readl_relaxed(base + MMCISTATUS);
352 base + MMCIMASK0);
362 base + MMCIMASK0);
366 writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR);
376 writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR);
380 writel_relaxed(cfgr, dlyb->base + DLYB_CFGR);
383 writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
395 ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr,
444 writel_relaxed(0, dlyb->base + DLYB_CR);
460 if (!dlyb || !dlyb->base)
472 writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR);
491 ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS,
497 host->base + MMCICLEAR);
529 host->pwr_reg = readl_relaxed(host->base + MMCIPOWER);
539 dlyb->base = base_dlyb;