Lines Matching defs:host
10 #include <linux/mmc/host.h>
54 static int sdmmc_idma_validate_data(struct mmci_host *host,
67 dev_err(mmc_dev(host->mmc),
75 dev_err(mmc_dev(host->mmc),
84 static int _sdmmc_idma_prep_data(struct mmci_host *host,
89 n_elem = dma_map_sg(mmc_dev(host->mmc),
95 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
102 static int sdmmc_idma_prep_data(struct mmci_host *host,
106 if (!next && data->host_cookie == host->next_cookie)
109 return _sdmmc_idma_prep_data(host, data);
112 static void sdmmc_idma_unprep_data(struct mmci_host *host,
115 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
119 static int sdmmc_idma_setup(struct mmci_host *host)
122 struct device *dev = mmc_dev(host->mmc);
128 host->dma_priv = idma;
130 if (host->variant->dma_lli) {
137 host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
139 host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
141 host->mmc->max_segs = 1;
142 host->mmc->max_seg_size = host->mmc->max_req_size;
145 return dma_set_max_seg_size(dev, host->mmc->max_seg_size);
148 static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
151 struct sdmmc_idma *idma = host->dma_priv;
153 struct mmc_data *data = host->data;
157 if (!host->variant->dma_lli || data->sg_len == 1) {
159 host->base + MMCI_STM32_IDMABASE0R);
161 host->base + MMCI_STM32_IDMACTRLR);
177 writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
178 writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
179 writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
180 writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
182 host->base + MMCI_STM32_IDMACTRLR);
187 static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data)
189 writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
192 sdmmc_idma_unprep_data(host, data, 0);
195 static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
199 if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
200 host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
209 if (desired >= host->mclk && !ddr) {
210 host->cclk = host->mclk;
212 clk = DIV_ROUND_UP(host->mclk, 2 * desired);
215 host->cclk = host->mclk / (2 * clk);
224 host->cclk = host->mclk / (2 * clk);
228 if (host->mmc->ios.power_mode == MMC_POWER_ON)
229 host->mmc->actual_clock = host->cclk;
231 host->mmc->actual_clock = 0;
233 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
235 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
239 clk |= host->clk_reg_add;
246 if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
248 if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) {
254 mmci_write_clkreg(host, clk);
266 static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
268 struct mmc_ios ios = host->mmc->ios;
269 struct sdmmc_dlyb *dlyb = host->variant_priv;
272 pwr = host->pwr_reg_add;
278 reset_control_assert(host->rst);
280 reset_control_deassert(host->rst);
288 mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr);
295 writel(MCI_IRQENABLE | host->variant->start_err,
296 host->base + MMCIMASK0);
299 pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN |
307 mmci_write_pwrreg(host, MCI_PWR_OFF | pwr);
309 mmci_write_pwrreg(host, MCI_PWR_ON | pwr);
313 static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
317 datactrl = mmci_dctrl_blksz(host);
319 if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
320 host->data->blocks == 1)
322 else if (host->data->stop && !host->mrq->sbc)
330 static bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
332 void __iomem *base = host->base;
350 if (!host->busy_status) {
351 writel_relaxed(mask | host->variant->busy_detect_mask,
353 host->busy_status = status &
360 if (host->busy_status) {
361 writel_relaxed(mask & ~host->variant->busy_detect_mask,
363 host->busy_status = 0;
366 writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR);
386 static int sdmmc_dlyb_lng_tuning(struct mmci_host *host)
388 struct sdmmc_dlyb *dlyb = host->variant_priv;
399 dev_warn(mmc_dev(host->mmc),
419 static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
421 struct sdmmc_dlyb *dlyb = host->variant_priv;
428 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
440 dev_err(mmc_dev(host->mmc), "no tuning point found\n");
449 dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n",
457 struct mmci_host *host = mmc_priv(mmc);
458 struct sdmmc_dlyb *dlyb = host->variant_priv;
463 if (sdmmc_dlyb_lng_tuning(host))
466 return sdmmc_dlyb_phase_tuning(host, opcode);
469 static void sdmmc_pre_sig_volt_vswitch(struct mmci_host *host)
472 writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR);
474 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN);
477 static int sdmmc_post_sig_volt_switch(struct mmci_host *host,
484 spin_lock_irqsave(&host->lock, flags);
486 host->pwr_reg & MCI_STM32_VSWITCHEN) {
487 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH);
488 spin_unlock_irqrestore(&host->lock, flags);
491 ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS,
497 host->base + MMCICLEAR);
498 spin_lock_irqsave(&host->lock, flags);
499 mmci_write_pwrreg(host, host->pwr_reg &
502 spin_unlock_irqrestore(&host->lock, flags);
522 void sdmmc_variant_init(struct mmci_host *host)
524 struct device_node *np = host->mmc->parent->of_node;
528 host->ops = &sdmmc_variant_ops;
529 host->pwr_reg = readl_relaxed(host->base + MMCIPOWER);
531 base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL);
535 dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL);
540 host->variant_priv = dlyb;
541 host->mmc_ops->execute_tuning = sdmmc_execute_tuning;