Lines Matching refs:host
3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
23 #include <linux/mmc/host.h>
47 static void mmci_variant_init(struct mmci_host *host);
48 static void ux500_variant_init(struct mmci_host *host);
49 static void ux500v2_variant_init(struct mmci_host *host);
337 struct mmci_host *host = mmc_priv(mmc);
341 spin_lock_irqsave(&host->lock, flags);
342 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
344 spin_unlock_irqrestore(&host->lock, flags);
349 static void mmci_reg_delay(struct mmci_host *host)
358 if (host->cclk < 25000000)
365 * This must be called with host->lock held
367 void mmci_write_clkreg(struct mmci_host *host, u32 clk)
369 if (host->clk_reg != clk) {
370 host->clk_reg = clk;
371 writel(clk, host->base + MMCICLOCK);
376 * This must be called with host->lock held
378 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
380 if (host->pwr_reg != pwr) {
381 host->pwr_reg = pwr;
382 writel(pwr, host->base + MMCIPOWER);
387 * This must be called with host->lock held
389 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
392 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
394 if (host->datactrl_reg != datactrl) {
395 host->datactrl_reg = datactrl;
396 writel(datactrl, host->base + MMCIDATACTRL);
401 * This must be called with host->lock held
403 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
405 struct variant_data *variant = host->variant;
409 host->cclk = 0;
413 host->cclk = host->mclk;
414 } else if (desired >= host->mclk) {
418 host->cclk = host->mclk;
426 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
429 host->cclk = host->mclk / (clk + 2);
435 clk = host->mclk / (2 * desired) - 1;
438 host->cclk = host->mclk / (2 * (clk + 1));
448 host->mmc->actual_clock = host->cclk;
450 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
452 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
455 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
456 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
459 mmci_write_clkreg(host, clk);
462 static void mmci_dma_release(struct mmci_host *host)
464 if (host->ops && host->ops->dma_release)
465 host->ops->dma_release(host);
467 host->use_dma = false;
470 static void mmci_dma_setup(struct mmci_host *host)
472 if (!host->ops || !host->ops->dma_setup)
475 if (host->ops->dma_setup(host))
479 host->next_cookie = 1;
481 host->use_dma = true;
487 static int mmci_validate_data(struct mmci_host *host,
490 struct variant_data *variant = host->variant;
495 dev_err(mmc_dev(host->mmc),
500 if (host->ops && host->ops->validate_data)
501 return host->ops->validate_data(host, data);
506 static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next)
510 if (!host->ops || !host->ops->prep_data)
513 err = host->ops->prep_data(host, data, next);
516 data->host_cookie = ++host->next_cookie < 0 ?
517 1 : host->next_cookie;
522 static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data,
525 if (host->ops && host->ops->unprep_data)
526 host->ops->unprep_data(host, data, err);
531 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
533 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
535 if (host->ops && host->ops->get_next_data)
536 host->ops->get_next_data(host, data);
539 static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
541 struct mmc_data *data = host->data;
544 if (!host->use_dma)
547 ret = mmci_prep_data(host, data, false);
551 if (!host->ops || !host->ops->dma_start)
555 dev_vdbg(mmc_dev(host->mmc),
559 ret = host->ops->dma_start(host, &datactrl);
564 mmci_write_datactrlreg(host, datactrl);
571 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
572 host->base + MMCIMASK0);
576 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
578 if (!host->use_dma)
581 if (host->ops && host->ops->dma_finalize)
582 host->ops->dma_finalize(host, data);
585 static void mmci_dma_error(struct mmci_host *host)
587 if (!host->use_dma)
590 if (host->ops && host->ops->dma_error)
591 host->ops->dma_error(host);
595 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
597 writel(0, host->base + MMCICOMMAND);
599 BUG_ON(host->data);
601 host->mrq = NULL;
602 host->cmd = NULL;
604 mmc_request_done(host->mmc, mrq);
607 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
609 void __iomem *base = host->base;
610 struct variant_data *variant = host->variant;
612 if (host->singleirq) {
624 host->mask1_reg = mask;
627 static void mmci_stop_data(struct mmci_host *host)
629 mmci_write_datactrlreg(host, 0);
630 mmci_set_mask1(host, 0);
631 host->data = NULL;
634 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
643 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
646 static u32 mmci_get_dctrl_cfg(struct mmci_host *host)
648 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host);
651 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host)
653 return MCI_DPSM_ENABLE | (host->data->blksz << 16);
656 static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
658 void __iomem *base = host->base;
664 * store the status in host->busy_status.
673 if (!host->busy_status && !(status & err_msk) &&
674 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
676 host->variant->busy_detect_mask,
679 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND);
694 if (host->busy_status &&
695 (status & host->variant->busy_detect_flag)) {
696 writel(host->variant->busy_detect_mask, base + MMCICLEAR);
706 if (host->busy_status) {
707 writel(host->variant->busy_detect_mask, base + MMCICLEAR);
710 ~host->variant->busy_detect_mask, base + MMCIMASK0);
711 host->busy_status = 0;
736 int mmci_dmae_setup(struct mmci_host *host)
741 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL);
745 host->dma_priv = dmae;
747 dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx");
754 dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx");
757 dev_warn(mmc_dev(host->mmc),
780 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
791 if (max_seg_size < host->mmc->max_seg_size)
792 host->mmc->max_seg_size = max_seg_size;
798 if (max_seg_size < host->mmc->max_seg_size)
799 host->mmc->max_seg_size = max_seg_size;
803 mmci_dmae_release(host);
814 void mmci_dmae_release(struct mmci_host *host)
816 struct mmci_dmae_priv *dmae = host->dma_priv;
825 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
827 struct mmci_dmae_priv *dmae = host->dma_priv;
839 void mmci_dmae_error(struct mmci_host *host)
841 struct mmci_dmae_priv *dmae = host->dma_priv;
843 if (!dma_inprogress(host))
846 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
848 host->dma_in_progress = false;
851 host->data->host_cookie = 0;
853 mmci_dma_unmap(host, host->data);
856 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data)
858 struct mmci_dmae_priv *dmae = host->dma_priv;
862 if (!dma_inprogress(host))
867 status = readl(host->base + MMCISTATUS);
880 mmci_dma_error(host);
884 mmci_dma_unmap(host, data);
892 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
893 mmci_dma_release(host);
896 host->dma_in_progress = false;
902 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
906 struct mmci_dmae_priv *dmae = host->dma_priv;
907 struct variant_data *variant = host->variant;
909 .src_addr = host->phybase + MMCIFIFO,
910 .dst_addr = host->phybase + MMCIFIFO,
948 if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz))
957 if (host->variant->qcom_dml)
977 int mmci_dmae_prep_data(struct mmci_host *host,
981 struct mmci_dmae_priv *dmae = host->dma_priv;
984 if (!host->use_dma)
988 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc);
994 return _mmci_dmae_prep_data(host, data, &dmae->cur,
998 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl)
1000 struct mmci_dmae_priv *dmae = host->dma_priv;
1003 host->dma_in_progress = true;
1006 host->dma_in_progress = false;
1016 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data)
1018 struct mmci_dmae_priv *dmae = host->dma_priv;
1021 if (!host->use_dma)
1032 void mmci_dmae_unprep_data(struct mmci_host *host,
1036 struct mmci_dmae_priv *dmae = host->dma_priv;
1038 if (!host->use_dma)
1041 mmci_dma_unmap(host, data);
1056 host->dma_in_progress = false;
1082 static void mmci_variant_init(struct mmci_host *host)
1084 host->ops = &mmci_variant_ops;
1087 static void ux500_variant_init(struct mmci_host *host)
1089 host->ops = &mmci_variant_ops;
1090 host->ops->busy_complete = ux500_busy_complete;
1093 static void ux500v2_variant_init(struct mmci_host *host)
1095 host->ops = &mmci_variant_ops;
1096 host->ops->busy_complete = ux500_busy_complete;
1097 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg;
1102 struct mmci_host *host = mmc_priv(mmc);
1110 if (mmci_validate_data(host, data))
1113 mmci_prep_data(host, data, true);
1119 struct mmci_host *host = mmc_priv(mmc);
1125 mmci_unprep_data(host, data, err);
1128 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
1130 struct variant_data *variant = host->variant;
1135 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
1138 host->data = data;
1139 host->size = data->blksz * data->blocks;
1142 clks = (unsigned long long)data->timeout_ns * host->cclk;
1147 base = host->base;
1149 writel(host->size, base + MMCIDATALENGTH);
1151 datactrl = host->ops->get_datactrl_cfg(host);
1152 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0;
1154 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
1166 (host->size < 8 ||
1167 (host->size <= 8 && host->mclk > 50000000)))
1168 clk = host->clk_reg & ~variant->clkreg_enable;
1170 clk = host->clk_reg | variant->clkreg_enable;
1172 mmci_write_clkreg(host, clk);
1175 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
1176 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
1183 if (!mmci_dma_start(host, datactrl))
1187 mmci_init_sg(host, data);
1197 if (host->size < variant->fifohalfsize)
1207 mmci_write_datactrlreg(host, datactrl);
1209 mmci_set_mask1(host, irqmask);
1213 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
1215 void __iomem *base = host->base;
1218 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1221 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) {
1223 mmci_reg_delay(host);
1226 if (host->variant->cmdreg_stop &&
1228 c |= host->variant->cmdreg_stop;
1230 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable;
1233 c |= host->variant->cmdreg_lrsp_crc;
1235 c |= host->variant->cmdreg_srsp_crc;
1237 c |= host->variant->cmdreg_srsp;
1240 if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) {
1244 if (cmd->busy_timeout > host->mmc->max_busy_timeout)
1245 clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk;
1247 clks = (unsigned long long)cmd->busy_timeout * host->cclk;
1250 writel_relaxed(clks, host->base + MMCIDATATIMER);
1253 if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE)
1254 host->ops->pre_sig_volt_switch(host);
1260 c |= host->variant->data_cmd_enable;
1262 host->cmd = cmd;
1268 static void mmci_stop_command(struct mmci_host *host)
1270 host->stop_abort.error = 0;
1271 mmci_start_command(host, &host->stop_abort, 0);
1275 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
1285 status_err = status & (host->variant->start_err |
1293 mmci_dma_error(host);
1298 * on the MMC bus, not on the host side. On reads, this
1302 if (!host->variant->datacnt_useless) {
1303 remain = readl(host->base + MMCIDATACNT);
1309 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
1322 if (success > host->variant->fifosize)
1323 success -= host->variant->fifosize;
1332 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
1335 mmci_dma_finalize(host, data);
1337 mmci_stop_data(host);
1344 if (host->variant->cmdreg_stop && data->error)
1345 mmci_stop_command(host);
1347 mmci_request_end(host, data->mrq);
1348 } else if (host->mrq->sbc && !data->error) {
1349 mmci_request_end(host, data->mrq);
1351 mmci_start_command(host, data->stop, 0);
1357 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
1361 void __iomem *base = host->base;
1367 sbc = (cmd == host->mrq->sbc);
1375 if (host->variant->busy_timeout && busy_resp)
1378 if (!((status | host->busy_status) &
1383 if (busy_resp && host->variant->busy_detect)
1384 if (!host->ops->busy_complete(host, status, err_msk))
1387 host->cmd = NULL;
1393 } else if (host->variant->busy_timeout && busy_resp &&
1396 host->irq_action = IRQ_WAKE_THREAD;
1405 if (host->data) {
1407 mmci_dma_error(host);
1409 mmci_stop_data(host);
1410 if (host->variant->cmdreg_stop && cmd->error) {
1411 mmci_stop_command(host);
1416 if (host->irq_action != IRQ_WAKE_THREAD)
1417 mmci_request_end(host, host->mrq);
1420 mmci_start_command(host, host->mrq->cmd, 0);
1421 } else if (!host->variant->datactrl_first &&
1423 mmci_start_data(host, cmd->data);
1427 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1429 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1432 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1439 return host->variant->fifohalfsize;
1446 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1448 void __iomem *base = host->base;
1450 u32 status = readl(host->base + MMCISTATUS);
1451 int host_remain = host->size;
1454 int count = host->get_rx_fifocnt(host, status, host_remain);
1494 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1496 struct variant_data *variant = host->variant;
1497 void __iomem *base = host->base;
1534 struct mmci_host *host = dev_id;
1535 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1536 struct variant_data *variant = host->variant;
1537 void __iomem *base = host->base;
1542 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1566 len = mmci_pio_read(host, buffer, remain);
1568 len = mmci_pio_write(host, buffer, remain, status);
1572 host->size -= len;
1587 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1588 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1596 if (host->size == 0) {
1597 mmci_set_mask1(host, 0);
1609 struct mmci_host *host = dev_id;
1612 spin_lock(&host->lock);
1613 host->irq_action = IRQ_HANDLED;
1616 status = readl(host->base + MMCISTATUS);
1618 if (host->singleirq) {
1619 if (status & host->mask1_reg)
1622 status &= ~host->variant->irq_pio_mask;
1629 status &= readl(host->base + MMCIMASK0);
1630 if (host->variant->busy_detect)
1631 writel(status & ~host->variant->busy_detect_mask,
1632 host->base + MMCICLEAR);
1634 writel(status, host->base + MMCICLEAR);
1636 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1638 if (host->variant->reversed_irq_handling) {
1639 mmci_data_irq(host, host->data, status);
1640 mmci_cmd_irq(host, host->cmd, status);
1642 mmci_cmd_irq(host, host->cmd, status);
1643 mmci_data_irq(host, host->data, status);
1650 if (host->variant->busy_detect_flag)
1651 status &= ~host->variant->busy_detect_flag;
1655 spin_unlock(&host->lock);
1657 return host->irq_action;
1668 struct mmci_host *host = dev_id;
1671 if (host->rst) {
1672 reset_control_assert(host->rst);
1674 reset_control_deassert(host->rst);
1677 spin_lock_irqsave(&host->lock, flags);
1678 writel(host->clk_reg, host->base + MMCICLOCK);
1679 writel(host->pwr_reg, host->base + MMCIPOWER);
1680 writel(MCI_IRQENABLE | host->variant->start_err,
1681 host->base + MMCIMASK0);
1683 host->irq_action = IRQ_HANDLED;
1684 mmci_request_end(host, host->mrq);
1685 spin_unlock_irqrestore(&host->lock, flags);
1687 return host->irq_action;
1692 struct mmci_host *host = mmc_priv(mmc);
1695 WARN_ON(host->mrq != NULL);
1697 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1703 spin_lock_irqsave(&host->lock, flags);
1705 host->mrq = mrq;
1708 mmci_get_next_data(host, mrq->data);
1711 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ))
1712 mmci_start_data(host, mrq->data);
1715 mmci_start_command(host, mrq->sbc, 0);
1717 mmci_start_command(host, mrq->cmd, 0);
1719 spin_unlock_irqrestore(&host->lock, flags);
1724 struct mmci_host *host = mmc_priv(mmc);
1727 if (!host->variant->busy_detect)
1730 if (host->variant->busy_timeout && mmc->actual_clock)
1739 struct mmci_host *host = mmc_priv(mmc);
1740 struct variant_data *variant = host->variant;
1745 if (host->plat->ios_handler &&
1746 host->plat->ios_handler(mmc_dev(mmc), ios))
1754 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1756 host->vqmmc_enabled = false;
1773 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1779 host->vqmmc_enabled = true;
1792 pwr |= host->pwr_reg_add;
1811 pinctrl_select_state(host->pinctrl, host->pins_opendrain);
1823 if (host->variant->explicit_mclk_control &&
1824 ios->clock != host->clock_cache) {
1825 ret = clk_set_rate(host->clk, ios->clock);
1827 dev_err(mmc_dev(host->mmc),
1830 host->mclk = clk_get_rate(host->clk);
1832 host->clock_cache = ios->clock;
1834 spin_lock_irqsave(&host->lock, flags);
1836 if (host->ops && host->ops->set_clkreg)
1837 host->ops->set_clkreg(host, ios->clock);
1839 mmci_set_clkreg(host, ios->clock);
1843 if (host->ops && host->ops->set_pwrreg)
1844 host->ops->set_pwrreg(host, pwr);
1846 mmci_write_pwrreg(host, pwr);
1848 mmci_reg_delay(host);
1850 spin_unlock_irqrestore(&host->lock, flags);
1855 struct mmci_host *host = mmc_priv(mmc);
1856 struct mmci_platform_data *plat = host->plat;
1863 status = plat->status(mmc_dev(host->mmc));
1870 struct mmci_host *host = mmc_priv(mmc);
1875 if (!ret && host->ops && host->ops->post_sig_volt_switch)
1876 ret = host->ops->post_sig_volt_switch(host, ios);
1898 struct mmci_host *host = mmc_priv(mmc);
1905 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1907 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1909 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1911 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1913 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1915 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1917 host->pwr_reg_add |= MCI_STM32_DIRPOL;
1919 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
1921 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
1937 struct mmci_host *host;
1961 host = mmc_priv(mmc);
1962 host->mmc = mmc;
1963 host->mmc_ops = &mmci_ops;
1971 host->pinctrl = devm_pinctrl_get(&dev->dev);
1972 if (IS_ERR(host->pinctrl)) {
1974 ret = PTR_ERR(host->pinctrl);
1978 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
1980 if (IS_ERR(host->pins_opendrain)) {
1982 ret = PTR_ERR(host->pins_opendrain);
1987 host->hw_designer = amba_manf(dev);
1988 host->hw_revision = amba_rev(dev);
1989 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1990 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1992 host->clk = devm_clk_get(&dev->dev, NULL);
1993 if (IS_ERR(host->clk)) {
1994 ret = PTR_ERR(host->clk);
1998 ret = clk_prepare_enable(host->clk);
2003 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
2005 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
2007 host->plat = plat;
2008 host->variant = variant;
2009 host->mclk = clk_get_rate(host->clk);
2015 if (host->mclk > variant->f_max) {
2016 ret = clk_set_rate(host->clk, variant->f_max);
2019 host->mclk = clk_get_rate(host->clk);
2021 host->mclk);
2024 host->phybase = dev->res.start;
2025 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
2026 if (IS_ERR(host->base)) {
2027 ret = PTR_ERR(host->base);
2032 variant->init(host);
2041 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
2043 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);
2045 mmc->f_min = clk_round_rate(host->clk, 100000);
2047 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
2057 min(host->mclk, mmc->f_max);
2060 fmax : min(host->mclk, fmax);
2065 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
2066 if (IS_ERR(host->rst)) {
2067 ret = PTR_ERR(host->rst);
2094 mmci_write_datactrlreg(host,
2095 host->variant->busy_dpsm_flag);
2104 host->stop_abort.opcode = MMC_STOP_TRANSMISSION;
2105 host->stop_abort.arg = 0;
2106 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC;
2140 spin_lock_init(&host->lock);
2142 writel(0, host->base + MMCIMASK0);
2145 writel(0, host->base + MMCIMASK1);
2147 writel(0xfff, host->base + MMCICLEAR);
2168 DRIVER_NAME " (cmd)", host);
2173 host->singleirq = true;
2176 IRQF_SHARED, DRIVER_NAME " (pio)", host);
2181 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
2190 mmci_dma_setup(host);
2203 clk_disable_unprepare(host->clk);
2214 struct mmci_host *host = mmc_priv(mmc);
2215 struct variant_data *variant = host->variant;
2225 writel(0, host->base + MMCIMASK0);
2228 writel(0, host->base + MMCIMASK1);
2230 writel(0, host->base + MMCICOMMAND);
2231 writel(0, host->base + MMCIDATACTRL);
2233 mmci_dma_release(host);
2234 clk_disable_unprepare(host->clk);
2240 static void mmci_save(struct mmci_host *host)
2244 spin_lock_irqsave(&host->lock, flags);
2246 writel(0, host->base + MMCIMASK0);
2247 if (host->variant->pwrreg_nopower) {
2248 writel(0, host->base + MMCIDATACTRL);
2249 writel(0, host->base + MMCIPOWER);
2250 writel(0, host->base + MMCICLOCK);
2252 mmci_reg_delay(host);
2254 spin_unlock_irqrestore(&host->lock, flags);
2257 static void mmci_restore(struct mmci_host *host)
2261 spin_lock_irqsave(&host->lock, flags);
2263 if (host->variant->pwrreg_nopower) {
2264 writel(host->clk_reg, host->base + MMCICLOCK);
2265 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
2266 writel(host->pwr_reg, host->base + MMCIPOWER);
2268 writel(MCI_IRQENABLE | host->variant->start_err,
2269 host->base + MMCIMASK0);
2270 mmci_reg_delay(host);
2272 spin_unlock_irqrestore(&host->lock, flags);
2281 struct mmci_host *host = mmc_priv(mmc);
2283 mmci_save(host);
2284 clk_disable_unprepare(host->clk);
2296 struct mmci_host *host = mmc_priv(mmc);
2297 clk_prepare_enable(host->clk);
2298 mmci_restore(host);