Lines Matching defs:host
18 #include <linux/mmc/host.h>
229 struct meson_host *host = mmc_priv(mmc);
240 if (host->dram_access_quirk)
310 static void meson_mmc_clk_gate(struct meson_host *host)
314 if (host->pins_clk_gate) {
315 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
321 cfg = readl(host->regs + SD_EMMC_CFG);
323 writel(cfg, host->regs + SD_EMMC_CFG);
327 static void meson_mmc_clk_ungate(struct meson_host *host)
331 if (host->pins_clk_gate)
332 pinctrl_select_default_state(host->dev);
335 cfg = readl(host->regs + SD_EMMC_CFG);
337 writel(cfg, host->regs + SD_EMMC_CFG);
340 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
343 struct mmc_host *mmc = host->mmc;
348 if (host->ddr == ddr && host->req_rate == rate)
352 meson_mmc_clk_gate(host);
353 host->req_rate = 0;
361 cfg = readl(host->regs + SD_EMMC_CFG);
363 writel(cfg, host->regs + SD_EMMC_CFG);
372 writel(cfg, host->regs + SD_EMMC_CFG);
373 host->ddr = ddr;
375 ret = clk_set_rate(host->mmc_clk, rate);
377 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
382 host->req_rate = rate;
383 mmc->actual_clock = clk_get_rate(host->mmc_clk);
387 host->req_rate >>= 1;
391 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
393 dev_dbg(host->dev, "requested rate was %lu\n", rate);
396 meson_mmc_clk_ungate(host);
406 static int meson_mmc_clk_init(struct meson_host *host)
418 clk_reg = CLK_ALWAYS_ON(host);
423 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
431 clk = devm_clk_get(host->dev, name);
433 return dev_err_probe(host->dev, PTR_ERR(clk),
440 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
444 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
451 mux->reg = host->regs + SD_EMMC_CLOCK;
456 host->mux_clk = devm_clk_register(host->dev, &mux->hw);
457 if (WARN_ON(IS_ERR(host->mux_clk)))
458 return PTR_ERR(host->mux_clk);
461 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
465 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
469 clk_parent[0] = __clk_get_name(host->mux_clk);
473 div->reg = host->regs + SD_EMMC_CLOCK;
479 host->mmc_clk = devm_clk_register(host->dev, &div->hw);
480 if (WARN_ON(IS_ERR(host->mmc_clk)))
481 return PTR_ERR(host->mmc_clk);
484 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
485 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
489 return clk_prepare_enable(host->mmc_clk);
492 static void meson_mmc_disable_resampling(struct meson_host *host)
494 unsigned int val = readl(host->regs + host->data->adjust);
497 writel(val, host->regs + host->data->adjust);
500 static void meson_mmc_reset_resampling(struct meson_host *host)
504 meson_mmc_disable_resampling(host);
506 val = readl(host->regs + host->data->adjust);
508 writel(val, host->regs + host->data->adjust);
513 struct meson_host *host = mmc_priv(mmc);
518 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
519 clk_get_rate(host->mmc_clk));
521 val = readl(host->regs + host->data->adjust);
523 writel(val, host->regs + host->data->adjust);
533 writel(val, host->regs + host->data->adjust);
543 meson_mmc_reset_resampling(host);
547 static int meson_mmc_prepare_ios_clock(struct meson_host *host,
563 return meson_mmc_clk_set(host, ios->clock, ddr);
566 static void meson_mmc_check_resampling(struct meson_host *host,
574 meson_mmc_disable_resampling(host);
581 struct meson_host *host = mmc_priv(mmc);
594 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
596 host->vqmmc_enabled = false;
608 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
612 dev_err(host->dev,
615 host->vqmmc_enabled = true;
633 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
638 val = readl(host->regs + SD_EMMC_CFG);
641 writel(val, host->regs + SD_EMMC_CFG);
643 meson_mmc_check_resampling(host, ios);
644 err = meson_mmc_prepare_ios_clock(host, ios);
646 dev_err(host->dev, "Failed to set clock: %d\n,", err);
648 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
654 struct meson_host *host = mmc_priv(mmc);
656 host->cmd = NULL;
657 if (host->needs_pre_post_req)
659 mmc_request_done(host->mmc, mrq);
664 struct meson_host *host = mmc_priv(mmc);
667 cfg = readl(host->regs + SD_EMMC_CFG);
671 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
679 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
684 writel(cfg, host->regs + SD_EMMC_CFG);
706 struct meson_host *host = mmc_priv(mmc);
707 struct sd_emmc_desc *desc = host->descs;
708 struct mmc_data *data = host->cmd->data;
731 desc[i].cmd_arg = host->cmd->arg;
738 start = host->descs_dma_addr | START_DESC_BUSY;
739 writel(start, host->regs + SD_EMMC_START);
743 static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data,
769 writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);
776 *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset);
791 struct meson_host *host = mmc_priv(mmc);
799 host->cmd = cmd;
830 WARN_ON(xfer_bytes > host->bounce_buf_size);
831 if (host->dram_access_quirk)
832 meson_mmc_copy_buffer(host, data, xfer_bytes, true);
835 host->bounce_buf, xfer_bytes);
839 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
847 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
848 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
849 writel(0, host->regs + SD_EMMC_CMD_RSP);
851 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
874 struct meson_host *host = mmc_priv(mmc);
875 host->needs_pre_post_req = mrq->data &&
883 if (host->dram_access_quirk && mrq->data) {
891 if (host->needs_pre_post_req) {
894 host->needs_pre_post_req = false;
897 if (host->needs_pre_post_req)
901 writel(0, host->regs + SD_EMMC_START);
908 struct meson_host *host = mmc_priv(mmc);
911 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
912 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
913 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
914 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
916 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
922 struct meson_host *host = dev_id;
928 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
929 raw_status = readl(host->regs + SD_EMMC_STATUS);
933 dev_dbg(host->dev,
939 if (WARN_ON(!host) || WARN_ON(!host->cmd))
943 writel(status, host->regs + SD_EMMC_STATUS);
945 cmd = host->cmd;
949 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
956 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
962 meson_mmc_read_resp(host->mmc, cmd);
965 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
979 u32 start = readl(host->regs + SD_EMMC_START);
982 writel(start, host->regs + SD_EMMC_START);
988 static int meson_mmc_wait_desc_stop(struct meson_host *host)
1000 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
1007 struct meson_host *host = dev_id;
1008 struct mmc_command *next_cmd, *cmd = host->cmd;
1016 meson_mmc_wait_desc_stop(host);
1017 meson_mmc_request_done(host->mmc, cmd->mrq);
1025 WARN_ON(xfer_bytes > host->bounce_buf_size);
1026 if (host->dram_access_quirk)
1027 meson_mmc_copy_buffer(host, data, xfer_bytes, false);
1030 host->bounce_buf, xfer_bytes);
1035 meson_mmc_start_cmd(host->mmc, next_cmd);
1037 meson_mmc_request_done(host->mmc, cmd->mrq);
1056 static void meson_mmc_cfg_init(struct meson_host *host)
1068 writel(cfg, host->regs + SD_EMMC_CFG);
1073 struct meson_host *host = mmc_priv(mmc);
1076 regval = readl(host->regs + SD_EMMC_STATUS);
1120 struct meson_host *host;
1127 host = mmc_priv(mmc);
1128 host->mmc = mmc;
1129 host->dev = &pdev->dev;
1130 dev_set_drvdata(&pdev->dev, host);
1133 host->dram_access_quirk = device_property_read_bool(&pdev->dev,
1137 host->vqmmc_enabled = false;
1146 host->data = (struct meson_mmc_data *)
1148 if (!host->data)
1156 host->regs = devm_ioremap_resource(&pdev->dev, res);
1157 if (IS_ERR(host->regs))
1158 return PTR_ERR(host->regs);
1160 host->irq = platform_get_irq(pdev, 0);
1161 if (host->irq < 0)
1162 return host->irq;
1164 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1165 if (IS_ERR(host->pinctrl))
1166 return PTR_ERR(host->pinctrl);
1168 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1170 if (IS_ERR(host->pins_clk_gate)) {
1173 host->pins_clk_gate = NULL;
1176 host->core_clk = devm_clk_get(&pdev->dev, "core");
1177 if (IS_ERR(host->core_clk))
1178 return PTR_ERR(host->core_clk);
1180 ret = clk_prepare_enable(host->core_clk);
1184 ret = meson_mmc_clk_init(host);
1189 meson_mmc_cfg_init(host);
1192 writel(0, host->regs + SD_EMMC_START);
1195 writel(0, host->regs + SD_EMMC_IRQ_EN);
1197 host->regs + SD_EMMC_STATUS);
1199 host->regs + SD_EMMC_IRQ_EN);
1201 ret = request_threaded_irq(host->irq, meson_mmc_irq,
1203 dev_name(&pdev->dev), host);
1208 if (host->dram_access_quirk) {
1229 if (host->dram_access_quirk) {
1236 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
1237 host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
1238 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
1241 host->bounce_buf_size = mmc->max_req_size;
1242 host->bounce_buf =
1243 dma_alloc_coherent(host->dev, host->bounce_buf_size,
1244 &host->bounce_dma_addr, GFP_KERNEL);
1245 if (host->bounce_buf == NULL) {
1246 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1252 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1253 &host->descs_dma_addr, GFP_KERNEL);
1254 if (!host->descs) {
1255 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1268 if (!host->dram_access_quirk)
1269 dma_free_coherent(host->dev, host->bounce_buf_size,
1270 host->bounce_buf, host->bounce_dma_addr);
1272 free_irq(host->irq, host);
1274 clk_disable_unprepare(host->mmc_clk);
1276 clk_disable_unprepare(host->core_clk);
1282 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1284 mmc_remove_host(host->mmc);
1287 writel(0, host->regs + SD_EMMC_IRQ_EN);
1288 free_irq(host->irq, host);
1290 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1291 host->descs, host->descs_dma_addr);
1293 if (!host->dram_access_quirk)
1294 dma_free_coherent(host->dev, host->bounce_buf_size,
1295 host->bounce_buf, host->bounce_dma_addr);
1297 clk_disable_unprepare(host->mmc_clk);
1298 clk_disable_unprepare(host->core_clk);