Lines Matching defs:host
18 #include <linux/mmc/host.h>
186 static void jz4740_mmc_write_irq_mask(struct jz4740_mmc_host *host,
189 if (host->version >= JZ_MMC_JZ4725B)
190 return writel(val, host->base + JZ_REG_MMC_IMASK);
192 return writew(val, host->base + JZ_REG_MMC_IMASK);
195 static void jz4740_mmc_write_irq_reg(struct jz4740_mmc_host *host,
198 if (host->version >= JZ_MMC_JZ4780)
199 writel(val, host->base + JZ_REG_MMC_IREG);
201 writew(val, host->base + JZ_REG_MMC_IREG);
204 static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host)
206 if (host->version >= JZ_MMC_JZ4780)
207 return readl(host->base + JZ_REG_MMC_IREG);
209 return readw(host->base + JZ_REG_MMC_IREG);
215 static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host)
217 if (!host->use_dma)
220 dma_release_channel(host->dma_tx);
221 dma_release_channel(host->dma_rx);
224 static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host)
226 host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx");
227 if (IS_ERR(host->dma_tx)) {
228 dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n");
229 return PTR_ERR(host->dma_tx);
232 host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx");
233 if (IS_ERR(host->dma_rx)) {
234 dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n");
235 dma_release_channel(host->dma_tx);
236 return PTR_ERR(host->dma_rx);
243 if (host->dma_tx) {
244 struct device *dev = host->dma_tx->device->dev;
247 if (max_seg_size < host->mmc->max_seg_size)
248 host->mmc->max_seg_size = max_seg_size;
251 if (host->dma_rx) {
252 struct device *dev = host->dma_rx->device->dev;
255 if (max_seg_size < host->mmc->max_seg_size)
256 host->mmc->max_seg_size = max_seg_size;
262 static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host,
265 return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx;
268 static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host,
271 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
281 static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host,
285 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
298 dev_err(mmc_dev(host->mmc),
309 static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host,
312 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
324 conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
327 conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
330 sg_count = jz4740_mmc_prepare_dma_data(host, data, COOKIE_MAPPED);
339 dev_err(mmc_dev(host->mmc),
352 jz4740_mmc_dma_unmap(host, data);
359 struct jz4740_mmc_host *host = mmc_priv(mmc);
362 if (!host->use_dma)
366 if (jz4740_mmc_prepare_dma_data(host, data, COOKIE_PREMAPPED) < 0)
374 struct jz4740_mmc_host *host = mmc_priv(mmc);
378 jz4740_mmc_dma_unmap(host, data);
381 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
389 static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
394 spin_lock_irqsave(&host->lock, flags);
396 host->irq_mask &= ~irq;
398 host->irq_mask |= irq;
400 jz4740_mmc_write_irq_mask(host, host->irq_mask);
401 spin_unlock_irqrestore(&host->lock, flags);
404 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
412 writew(val, host->base + JZ_REG_MMC_STRPCL);
415 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
420 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
422 status = readl(host->base + JZ_REG_MMC_STATUS);
426 static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
431 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
434 status = readl(host->base + JZ_REG_MMC_STATUS);
438 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
443 req = host->req;
445 host->req = NULL;
448 jz4740_mmc_dma_unmap(host, data);
449 mmc_request_done(host->mmc, req);
452 static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
459 status = jz4740_mmc_read_irq_reg(host);
463 set_bit(0, &host->waiting);
464 mod_timer(&host->timeout_timer,
466 jz4740_mmc_set_irq_enabled(host, irq, true);
473 static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
478 status = readl(host->base + JZ_REG_MMC_STATUS);
481 host->req->cmd->error = -ETIMEDOUT;
484 host->req->cmd->error = -EIO;
489 host->req->cmd->error = -ETIMEDOUT;
492 host->req->cmd->error = -EIO;
498 static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
501 struct sg_mapping_iter *miter = &host->miter;
502 void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
513 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
529 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
553 static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
556 struct sg_mapping_iter *miter = &host->miter;
557 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
570 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
588 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
612 status = readl(host->base + JZ_REG_MMC_STATUS);
615 status = readl(host->base + JZ_REG_MMC_STATUS);
630 struct jz4740_mmc_host *host = from_timer(host, t, timeout_timer);
632 if (!test_and_clear_bit(0, &host->waiting))
635 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
637 host->req->cmd->error = -ETIMEDOUT;
638 jz4740_mmc_request_done(host);
641 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
646 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
664 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
667 uint32_t cmdat = host->cmdat;
669 host->cmdat &= ~JZ_MMC_CMDAT_INIT;
670 jz4740_mmc_clock_disable(host);
672 host->cmd = cmd;
696 if (host->use_dma) {
706 if (host->version >= JZ_MMC_JZ4780) {
708 host->base + JZ_REG_MMC_DMAC);
712 } else if (host->version >= JZ_MMC_JZ4780) {
713 writel(0, host->base + JZ_REG_MMC_DMAC);
716 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
717 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
720 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
721 writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
722 writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
724 jz4740_mmc_clock_enable(host, 1);
727 static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
729 struct mmc_command *cmd = host->req->cmd;
738 sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
744 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
745 struct mmc_command *cmd = host->req->cmd;
746 struct mmc_request *req = host->req;
751 host->state = JZ4740_MMC_STATE_DONE;
753 switch (host->state) {
756 jz4740_mmc_read_response(host, cmd);
761 jz_mmc_prepare_data_transfer(host);
765 if (host->use_dma) {
772 timeout = jz4740_mmc_start_dma_transfer(host, data);
780 timeout = jz4740_mmc_read_data(host, data);
782 timeout = jz4740_mmc_write_data(host, data);
785 host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
789 jz4740_mmc_transfer_check_state(host, data);
791 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
793 host->state = JZ4740_MMC_STATE_SEND_STOP;
796 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
803 jz4740_mmc_send_command(host, req->stop);
806 timeout = jz4740_mmc_poll_irq(host,
809 host->state = JZ4740_MMC_STATE_DONE;
818 jz4740_mmc_request_done(host);
825 struct jz4740_mmc_host *host = devid;
826 struct mmc_command *cmd = host->cmd;
829 status = readl(host->base + JZ_REG_MMC_STATUS);
830 irq_reg = jz4740_mmc_read_irq_reg(host);
833 irq_reg &= ~host->irq_mask;
839 jz4740_mmc_write_irq_reg(host, tmp & ~irq_reg);
842 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_SDIO);
843 mmc_signal_sdio_irq(host->mmc);
847 if (host->req && cmd && irq_reg) {
848 if (test_and_clear_bit(0, &host->waiting)) {
849 del_timer(&host->timeout_timer);
862 jz4740_mmc_set_irq_enabled(host, irq_reg, false);
863 jz4740_mmc_write_irq_reg(host, irq_reg);
872 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
877 jz4740_mmc_clock_disable(host);
878 clk_set_rate(host->clk, host->mmc->f_max);
880 real_rate = clk_get_rate(host->clk);
887 writew(div, host->base + JZ_REG_MMC_CLKRT);
890 if (host->version >= JZ_MMC_X1000) {
894 host->base + JZ_REG_MMC_LPM);
895 } else if (host->version >= JZ_MMC_JZ4760) {
898 host->base + JZ_REG_MMC_LPM);
899 } else if (host->version >= JZ_MMC_JZ4725B)
901 host->base + JZ_REG_MMC_LPM);
909 struct jz4740_mmc_host *host = mmc_priv(mmc);
911 host->req = req;
913 jz4740_mmc_write_irq_reg(host, ~0);
914 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
916 host->state = JZ4740_MMC_STATE_READ_RESPONSE;
917 set_bit(0, &host->waiting);
918 mod_timer(&host->timeout_timer,
920 jz4740_mmc_send_command(host, req->cmd);
925 struct jz4740_mmc_host *host = mmc_priv(mmc);
927 jz4740_mmc_set_clock_rate(host, ios->clock);
931 jz4740_mmc_reset(host);
934 host->cmdat |= JZ_MMC_CMDAT_INIT;
935 clk_prepare_enable(host->clk);
942 clk_disable_unprepare(host->clk);
948 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
951 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
952 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
955 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
956 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_8BIT;
965 struct jz4740_mmc_host *host = mmc_priv(mmc);
966 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
993 struct jz4740_mmc_host *host;
998 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
1002 host = mmc_priv(mmc);
1006 host->version = (enum jz4740_mmc_version)match->data;
1009 host->version = JZ_MMC_JZ4740;
1020 host->irq = platform_get_irq(pdev, 0);
1021 if (host->irq < 0) {
1022 ret = host->irq;
1026 host->clk = devm_clk_get(&pdev->dev, "mmc");
1027 if (IS_ERR(host->clk)) {
1028 ret = PTR_ERR(host->clk);
1033 host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1034 host->base = devm_ioremap_resource(&pdev->dev, host->mem_res);
1035 if (IS_ERR(host->base)) {
1036 ret = PTR_ERR(host->base);
1051 if (host->version == JZ_MMC_JZ4760 && mmc->f_max > JZ_MMC_CLK_RATE)
1070 host->mmc = mmc;
1071 host->pdev = pdev;
1072 spin_lock_init(&host->lock);
1073 host->irq_mask = ~0;
1075 jz4740_mmc_reset(host);
1077 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
1078 dev_name(&pdev->dev), host);
1084 jz4740_mmc_clock_disable(host);
1085 timer_setup(&host->timeout_timer, jz4740_mmc_timeout, 0);
1087 ret = jz4740_mmc_acquire_dma_channels(host);
1090 host->use_dma = !ret;
1092 platform_set_drvdata(pdev, host);
1096 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
1102 host->use_dma ? "DMA" : "PIO",
1109 if (host->use_dma)
1110 jz4740_mmc_release_dma_channels(host);
1112 free_irq(host->irq, host);
1121 struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
1123 del_timer_sync(&host->timeout_timer);
1124 jz4740_mmc_set_irq_enabled(host, 0xff, false);
1125 jz4740_mmc_reset(host);
1127 mmc_remove_host(host->mmc);
1129 free_irq(host->irq, host);
1131 if (host->use_dma)
1132 jz4740_mmc_release_dma_channels(host);
1134 mmc_free_host(host->mmc);