Lines Matching refs:host
29 #include <linux/mmc/host.h>
116 spin_lock_bh(&slot->host->lock);
142 spin_unlock_bh(&slot->host->lock);
150 struct dw_mci *host = s->private;
152 pm_runtime_get_sync(host->dev);
154 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
155 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
156 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
157 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
158 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
159 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
161 pm_runtime_put_autosuspend(host->dev);
170 struct dw_mci *host = slot->host;
177 debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops);
179 debugfs_create_u32("state", S_IRUSR, root, &host->state);
181 &host->pending_events);
183 &host->completed_events);
187 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
191 ctrl = mci_readl(host, CTRL);
193 mci_writel(host, CTRL, ctrl);
196 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
199 dev_err(host->dev,
208 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
222 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
226 dev_err(host->dev, "Busy; trying anyway\n");
232 struct dw_mci *host = slot->host;
235 mci_writel(host, CMDARG, arg);
237 dw_mci_wait_while_busy(host, cmd);
238 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
240 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
251 struct dw_mci *host = slot->host;
273 WARN_ON(slot->host->state != STATE_SENDING_CMD);
274 slot->host->state = STATE_SENDING_CMD11;
287 clk_en_a = mci_readl(host, CLKENA);
289 mci_writel(host, CLKENA, clk_en_a);
316 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
324 stop = &host->stop_abort;
349 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
355 static inline void dw_mci_set_cto(struct dw_mci *host)
362 cto_clks = mci_readl(host, TMOUT) & 0xff;
363 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
368 host->bus_hz);
386 spin_lock_irqsave(&host->irq_lock, irqflags);
387 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
388 mod_timer(&host->cto_timer,
390 spin_unlock_irqrestore(&host->irq_lock, irqflags);
393 static void dw_mci_start_command(struct dw_mci *host,
396 host->cmd = cmd;
397 dev_vdbg(host->dev,
401 mci_writel(host, CMDARG, cmd->arg);
403 dw_mci_wait_while_busy(host, cmd_flags);
405 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
409 dw_mci_set_cto(host);
412 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
414 struct mmc_command *stop = &host->stop_abort;
416 dw_mci_start_command(host, stop, host->stop_cmdr);
420 static void dw_mci_stop_dma(struct dw_mci *host)
422 if (host->using_dma) {
423 host->dma_ops->stop(host);
424 host->dma_ops->cleanup(host);
428 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
431 static void dw_mci_dma_cleanup(struct dw_mci *host)
433 struct mmc_data *data = host->data;
436 dma_unmap_sg(host->dev,
444 static void dw_mci_idmac_reset(struct dw_mci *host)
446 u32 bmod = mci_readl(host, BMOD);
449 mci_writel(host, BMOD, bmod);
452 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
457 temp = mci_readl(host, CTRL);
460 mci_writel(host, CTRL, temp);
463 temp = mci_readl(host, BMOD);
466 mci_writel(host, BMOD, temp);
471 struct dw_mci *host = arg;
472 struct mmc_data *data = host->data;
474 dev_vdbg(host->dev, "DMA complete\n");
476 if ((host->use_dma == TRANS_MODE_EDMAC) &&
479 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
484 host->dma_ops->cleanup(host);
491 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
492 tasklet_schedule(&host->tasklet);
496 static int dw_mci_idmac_init(struct dw_mci *host)
500 if (host->dma_64bit_address == 1) {
503 host->ring_size =
507 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
509 p->des6 = (host->sg_dma +
513 p->des7 = (u64)(host->sg_dma +
524 p->des6 = host->sg_dma & 0xffffffff;
525 p->des7 = (u64)host->sg_dma >> 32;
531 host->ring_size =
535 for (i = 0, p = host->sg_cpu;
536 i < host->ring_size - 1;
538 p->des3 = cpu_to_le32(host->sg_dma +
545 p->des3 = cpu_to_le32(host->sg_dma);
549 dw_mci_idmac_reset(host);
551 if (host->dma_64bit_address == 1) {
553 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
554 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
558 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
559 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
563 mci_writel(host, IDSTS, IDMAC_INT_CLR);
564 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
568 mci_writel(host, DBADDR, host->sg_dma);
574 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
583 desc_first = desc_last = desc = host->sg_cpu;
639 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
640 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
641 dw_mci_idmac_init(host);
646 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
655 desc_first = desc_last = desc = host->sg_cpu;
713 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
714 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
715 dw_mci_idmac_init(host);
719 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
724 if (host->dma_64bit_address == 1)
725 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
727 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
736 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
737 dw_mci_idmac_reset(host);
740 temp = mci_readl(host, CTRL);
742 mci_writel(host, CTRL, temp);
748 temp = mci_readl(host, BMOD);
750 mci_writel(host, BMOD, temp);
753 mci_writel(host, PLDMND, 1);
767 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
769 dmaengine_terminate_async(host->dms->ch);
772 static int dw_mci_edmac_start_dma(struct dw_mci *host,
777 struct scatterlist *sgl = host->data->sg;
779 u32 sg_elems = host->data->sg_len;
781 u32 fifo_offset = host->fifo_reg - host->regs;
786 cfg.dst_addr = host->phy_regs + fifo_offset;
792 fifoth_val = mci_readl(host, FIFOTH);
796 if (host->data->flags & MMC_DATA_WRITE)
801 ret = dmaengine_slave_config(host->dms->ch, &cfg);
803 dev_err(host->dev, "Failed to config edmac.\n");
807 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
811 dev_err(host->dev, "Can't prepare slave sg.\n");
817 desc->callback_param = (void *)host;
821 if (host->data->flags & MMC_DATA_WRITE)
822 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
825 dma_async_issue_pending(host->dms->ch);
830 static int dw_mci_edmac_init(struct dw_mci *host)
833 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
834 if (!host->dms)
837 host->dms->ch = dma_request_chan(host->dev, "rx-tx");
838 if (IS_ERR(host->dms->ch)) {
839 int ret = PTR_ERR(host->dms->ch);
841 dev_err(host->dev, "Failed to get external DMA channel.\n");
842 kfree(host->dms);
843 host->dms = NULL;
850 static void dw_mci_edmac_exit(struct dw_mci *host)
852 if (host->dms) {
853 if (host->dms->ch) {
854 dma_release_channel(host->dms->ch);
855 host->dms->ch = NULL;
857 kfree(host->dms);
858 host->dms = NULL;
871 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
897 sg_len = dma_map_sg(host->dev,
915 if (!slot->host->use_dma || !data)
921 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
933 if (!slot->host->use_dma || !data)
937 dma_unmap_sg(slot->host->dev,
948 struct dw_mci *host = slot->host;
971 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
974 spin_lock_bh(&host->lock);
980 spin_unlock_bh(&host->lock);
985 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
989 u32 fifo_width = 1 << host->data_shift;
995 if (!host->use_dma)
998 tx_wmark = (host->fifo_depth) / 2;
999 tx_wmark_invers = host->fifo_depth - tx_wmark;
1022 mci_writel(host, FIFOTH, fifoth_val);
1025 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1036 if (host->verid < DW_MMC_240A ||
1037 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1045 host->timing != MMC_TIMING_MMC_HS400)
1053 if (host->timing != MMC_TIMING_MMC_HS200 &&
1054 host->timing != MMC_TIMING_UHS_SDR104 &&
1055 host->timing != MMC_TIMING_MMC_HS400)
1058 blksz_depth = blksz / (1 << host->data_shift);
1059 fifo_depth = host->fifo_depth;
1070 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1074 mci_writel(host, CDTHRCTL, 0);
1077 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1083 host->using_dma = 0;
1086 if (!host->use_dma)
1089 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1091 host->dma_ops->stop(host);
1095 host->using_dma = 1;
1097 if (host->use_dma == TRANS_MODE_IDMAC)
1098 dev_vdbg(host->dev,
1100 (unsigned long)host->sg_cpu,
1101 (unsigned long)host->sg_dma,
1109 if (host->prev_blksz != data->blksz)
1110 dw_mci_adjust_fifoth(host, data);
1113 temp = mci_readl(host, CTRL);
1115 mci_writel(host, CTRL, temp);
1118 spin_lock_irqsave(&host->irq_lock, irqflags);
1119 temp = mci_readl(host, INTMASK);
1121 mci_writel(host, INTMASK, temp);
1122 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1124 if (host->dma_ops->start(host, sg_len)) {
1125 host->dma_ops->stop(host);
1127 dev_dbg(host->dev,
1136 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1144 WARN_ON(host->data);
1145 host->sg = NULL;
1146 host->data = data;
1149 host->dir_status = DW_MCI_RECV_STATUS;
1151 host->dir_status = DW_MCI_SEND_STATUS;
1153 dw_mci_ctrl_thld(host, data);
1155 if (dw_mci_submit_data_dma(host, data)) {
1156 if (host->data->flags & MMC_DATA_READ)
1161 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1162 host->sg = data->sg;
1163 host->part_buf_start = 0;
1164 host->part_buf_count = 0;
1166 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1168 spin_lock_irqsave(&host->irq_lock, irqflags);
1169 temp = mci_readl(host, INTMASK);
1171 mci_writel(host, INTMASK, temp);
1172 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1174 temp = mci_readl(host, CTRL);
1176 mci_writel(host, CTRL, temp);
1184 if (host->wm_aligned)
1185 dw_mci_adjust_fifoth(host, data);
1187 mci_writel(host, FIFOTH, host->fifoth_val);
1188 host->prev_blksz = 0;
1195 host->prev_blksz = data->blksz;
1201 struct dw_mci *host = slot->host;
1208 if (host->state == STATE_WAITING_CMD11_DONE)
1214 mci_writel(host, CLKENA, 0);
1216 } else if (clock != host->current_speed || force_clkinit) {
1217 div = host->bus_hz / clock;
1218 if (host->bus_hz % clock && host->bus_hz > clock)
1225 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1234 slot->id, host->bus_hz, clock,
1235 div ? ((host->bus_hz / div) >> 1) :
1236 host->bus_hz, div);
1248 mci_writel(host, CLKENA, 0);
1249 mci_writel(host, CLKSRC, 0);
1255 mci_writel(host, CLKDIV, div);
1264 mci_writel(host, CLKENA, clk_en_a);
1271 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
1272 host->bus_hz;
1275 host->current_speed = clock;
1278 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1281 static void __dw_mci_start_request(struct dw_mci *host,
1291 host->mrq = mrq;
1293 host->pending_events = 0;
1294 host->completed_events = 0;
1295 host->cmd_status = 0;
1296 host->data_status = 0;
1297 host->dir_status = 0;
1301 mci_writel(host, TMOUT, 0xFFFFFFFF);
1302 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1303 mci_writel(host, BLKSIZ, data->blksz);
1313 dw_mci_submit_data(host, data);
1317 dw_mci_start_command(host, cmd, cmdflags);
1332 spin_lock_irqsave(&host->irq_lock, irqflags);
1333 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1334 mod_timer(&host->cmd11_timer,
1336 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1339 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1342 static void dw_mci_start_request(struct dw_mci *host,
1349 __dw_mci_start_request(host, slot, cmd);
1352 /* must be called with host->lock held */
1353 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1357 host->state);
1361 if (host->state == STATE_WAITING_CMD11_DONE) {
1369 host->state = STATE_IDLE;
1372 if (host->state == STATE_IDLE) {
1373 host->state = STATE_SENDING_CMD;
1374 dw_mci_start_request(host, slot);
1376 list_add_tail(&slot->queue_node, &host->queue);
1383 struct dw_mci *host = slot->host;
1399 spin_lock_bh(&host->lock);
1401 dw_mci_queue_request(host, slot, mrq);
1403 spin_unlock_bh(&host->lock);
1409 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1425 regs = mci_readl(slot->host, UHS_REG);
1435 mci_writel(slot->host, UHS_REG, regs);
1436 slot->host->timing = ios->timing;
1445 drv_data->set_ios(slot->host, ios);
1453 dev_err(slot->host->dev,
1460 regs = mci_readl(slot->host, PWREN);
1462 mci_writel(slot->host, PWREN, regs);
1465 if (!slot->host->vqmmc_enabled) {
1469 dev_err(slot->host->dev,
1472 slot->host->vqmmc_enabled = true;
1476 slot->host->vqmmc_enabled = true;
1480 dw_mci_ctrl_reset(slot->host,
1495 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1497 slot->host->vqmmc_enabled = false;
1499 regs = mci_readl(slot->host, PWREN);
1501 mci_writel(slot->host, PWREN, regs);
1507 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1508 slot->host->state = STATE_IDLE;
1520 status = mci_readl(slot->host, STATUS);
1528 struct dw_mci *host = slot->host;
1529 const struct dw_mci_drv_data *drv_data = host->drv_data;
1542 uhs = mci_readl(host, UHS_REG);
1557 mci_writel(host, UHS_REG, uhs);
1573 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1584 struct dw_mci *host = slot->host;
1587 if (host->use_dma == TRANS_MODE_IDMAC)
1588 dw_mci_idmac_reset(host);
1590 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1600 reset = mci_readl(host, RST_N);
1602 mci_writel(host, RST_N, reset);
1605 mci_writel(host, RST_N, reset);
1612 struct dw_mci *host = slot->host;
1624 clk_en_a_old = mci_readl(host, CLKENA);
1636 mci_writel(host, CLKENA, clk_en_a);
1645 struct dw_mci *host = slot->host;
1649 spin_lock_irqsave(&host->irq_lock, irqflags);
1652 int_mask = mci_readl(host, INTMASK);
1657 mci_writel(host, INTMASK, int_mask);
1659 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1665 struct dw_mci *host = slot->host;
1671 pm_runtime_get_noresume(host->dev);
1673 pm_runtime_put_noidle(host->dev);
1686 struct dw_mci *host = slot->host;
1687 const struct dw_mci_drv_data *drv_data = host->drv_data;
1699 struct dw_mci *host = slot->host;
1700 const struct dw_mci_drv_data *drv_data = host->drv_data;
1703 return drv_data->prepare_hs400_tuning(host, ios);
1708 static bool dw_mci_reset(struct dw_mci *host)
1718 if (host->sg) {
1719 sg_miter_stop(&host->sg_miter);
1720 host->sg = NULL;
1723 if (host->use_dma)
1726 if (dw_mci_ctrl_reset(host, flags)) {
1731 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1733 if (!host->use_dma) {
1739 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1743 dev_err(host->dev,
1750 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1754 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1755 dev_err(host->dev,
1762 if (host->use_dma == TRANS_MODE_IDMAC)
1764 dw_mci_idmac_init(host);
1770 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1792 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1793 __releases(&host->lock)
1794 __acquires(&host->lock)
1797 struct mmc_host *prev_mmc = host->slot->mmc;
1799 WARN_ON(host->cmd || host->data);
1801 host->slot->mrq = NULL;
1802 host->mrq = NULL;
1803 if (!list_empty(&host->queue)) {
1804 slot = list_entry(host->queue.next,
1807 dev_vdbg(host->dev, "list not empty: %s is next\n",
1809 host->state = STATE_SENDING_CMD;
1810 dw_mci_start_request(host, slot);
1812 dev_vdbg(host->dev, "list empty\n");
1814 if (host->state == STATE_SENDING_CMD11)
1815 host->state = STATE_WAITING_CMD11_DONE;
1817 host->state = STATE_IDLE;
1820 spin_unlock(&host->lock);
1822 spin_lock(&host->lock);
1825 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1827 u32 status = host->cmd_status;
1829 host->cmd_status = 0;
1834 cmd->resp[3] = mci_readl(host, RESP0);
1835 cmd->resp[2] = mci_readl(host, RESP1);
1836 cmd->resp[1] = mci_readl(host, RESP2);
1837 cmd->resp[0] = mci_readl(host, RESP3);
1839 cmd->resp[0] = mci_readl(host, RESP0);
1858 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1860 u32 status = host->data_status;
1868 if (host->dir_status ==
1877 } else if (host->dir_status ==
1886 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1892 dw_mci_reset(host);
1901 static void dw_mci_set_drto(struct dw_mci *host)
1908 drto_clks = mci_readl(host, TMOUT) >> 8;
1909 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
1914 host->bus_hz);
1919 spin_lock_irqsave(&host->irq_lock, irqflags);
1920 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1921 mod_timer(&host->dto_timer,
1923 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1926 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1928 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1938 WARN_ON(del_timer_sync(&host->cto_timer));
1939 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1944 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
1946 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1950 WARN_ON(del_timer_sync(&host->dto_timer));
1951 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1958 struct dw_mci *host = (struct dw_mci *)priv;
1966 spin_lock(&host->lock);
1968 state = host->state;
1969 data = host->data;
1970 mrq = host->mrq;
1982 if (!dw_mci_clear_pending_cmd_complete(host))
1985 cmd = host->cmd;
1986 host->cmd = NULL;
1987 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1988 err = dw_mci_command_complete(host, cmd);
1990 __dw_mci_start_request(host, host->slot,
2018 host->dir_status == DW_MCI_RECV_STATUS) {
2023 send_stop_abort(host, data);
2024 dw_mci_stop_dma(host);
2030 dw_mci_request_end(host, mrq);
2047 &host->pending_events)) {
2048 if (!(host->data_status & (SDMMC_INT_DRTO |
2050 send_stop_abort(host, data);
2051 dw_mci_stop_dma(host);
2057 &host->pending_events)) {
2062 if (host->dir_status == DW_MCI_RECV_STATUS)
2063 dw_mci_set_drto(host);
2067 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2083 &host->pending_events)) {
2084 if (!(host->data_status & (SDMMC_INT_DRTO |
2086 send_stop_abort(host, data);
2087 dw_mci_stop_dma(host);
2096 if (!dw_mci_clear_pending_data_complete(host)) {
2102 if (host->dir_status == DW_MCI_RECV_STATUS)
2103 dw_mci_set_drto(host);
2107 host->data = NULL;
2108 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2109 err = dw_mci_data_complete(host, data);
2115 dw_mci_request_end(host, mrq);
2121 send_stop_abort(host, data);
2133 &host->pending_events)) {
2134 host->cmd = NULL;
2135 dw_mci_request_end(host, mrq);
2149 if (!dw_mci_clear_pending_cmd_complete(host))
2154 dw_mci_reset(host);
2156 host->cmd = NULL;
2157 host->data = NULL;
2160 dw_mci_command_complete(host, mrq->stop);
2162 host->cmd_status = 0;
2164 dw_mci_request_end(host, mrq);
2169 &host->pending_events))
2177 host->state = state;
2179 spin_unlock(&host->lock);
2184 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2186 memcpy((void *)&host->part_buf, buf, cnt);
2187 host->part_buf_count = cnt;
2191 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2193 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2194 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2195 host->part_buf_count += cnt;
2200 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2202 cnt = min_t(int, cnt, host->part_buf_count);
2204 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2206 host->part_buf_count -= cnt;
2207 host->part_buf_start += cnt;
2213 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2215 memcpy(buf, &host->part_buf, cnt);
2216 host->part_buf_start = cnt;
2217 host->part_buf_count = (1 << host->data_shift) - cnt;
2220 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2222 struct mmc_data *data = host->data;
2226 if (unlikely(host->part_buf_count)) {
2227 int len = dw_mci_push_part_bytes(host, buf, cnt);
2231 if (host->part_buf_count == 2) {
2232 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2233 host->part_buf_count = 0;
2249 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2257 mci_fifo_writew(host->fifo_reg, *pdata++);
2262 dw_mci_set_part_bytes(host, buf, cnt);
2266 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2270 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2282 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2294 *pdata++ = mci_fifo_readw(host->fifo_reg);
2298 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2299 dw_mci_pull_final_bytes(host, buf, cnt);
2303 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2305 struct mmc_data *data = host->data;
2309 if (unlikely(host->part_buf_count)) {
2310 int len = dw_mci_push_part_bytes(host, buf, cnt);
2314 if (host->part_buf_count == 4) {
2315 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2316 host->part_buf_count = 0;
2332 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2340 mci_fifo_writel(host->fifo_reg, *pdata++);
2345 dw_mci_set_part_bytes(host, buf, cnt);
2349 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2353 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2365 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2377 *pdata++ = mci_fifo_readl(host->fifo_reg);
2381 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2382 dw_mci_pull_final_bytes(host, buf, cnt);
2386 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2388 struct mmc_data *data = host->data;
2392 if (unlikely(host->part_buf_count)) {
2393 int len = dw_mci_push_part_bytes(host, buf, cnt);
2398 if (host->part_buf_count == 8) {
2399 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2400 host->part_buf_count = 0;
2416 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2424 mci_fifo_writeq(host->fifo_reg, *pdata++);
2429 dw_mci_set_part_bytes(host, buf, cnt);
2433 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2437 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2449 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2462 *pdata++ = mci_fifo_readq(host->fifo_reg);
2466 host->part_buf = mci_fifo_readq(host->fifo_reg);
2467 dw_mci_pull_final_bytes(host, buf, cnt);
2471 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2476 len = dw_mci_pull_part_bytes(host, buf, cnt);
2483 host->pull_data(host, buf, cnt);
2486 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2488 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2491 struct mmc_data *data = host->data;
2492 int shift = host->data_shift;
2501 host->sg = sg_miter->piter.sg;
2507 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2508 << shift) + host->part_buf_count;
2512 dw_mci_pull_data(host, (void *)(buf + offset), len);
2519 status = mci_readl(host, MINTSTS);
2520 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2523 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2535 host->sg = NULL;
2537 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2540 static void dw_mci_write_data_pio(struct dw_mci *host)
2542 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2545 struct mmc_data *data = host->data;
2546 int shift = host->data_shift;
2549 unsigned int fifo_depth = host->fifo_depth;
2556 host->sg = sg_miter->piter.sg;
2563 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2564 << shift) - host->part_buf_count;
2568 host->push_data(host, (void *)(buf + offset), len);
2575 status = mci_readl(host, MINTSTS);
2576 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2589 host->sg = NULL;
2591 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2594 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2596 del_timer(&host->cto_timer);
2598 if (!host->cmd_status)
2599 host->cmd_status = status;
2603 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2604 tasklet_schedule(&host->tasklet);
2607 static void dw_mci_handle_cd(struct dw_mci *host)
2609 struct dw_mci_slot *slot = host->slot;
2614 msecs_to_jiffies(host->pdata->detect_delay_ms));
2619 struct dw_mci *host = dev_id;
2621 struct dw_mci_slot *slot = host->slot;
2624 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2628 if ((host->state == STATE_SENDING_CMD11) &&
2630 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2637 spin_lock_irqsave(&host->irq_lock, irqflags);
2638 dw_mci_cmd_interrupt(host, pending);
2639 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2641 del_timer(&host->cmd11_timer);
2645 spin_lock_irqsave(&host->irq_lock, irqflags);
2647 del_timer(&host->cto_timer);
2648 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2649 host->cmd_status = pending;
2651 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2653 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2658 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2659 host->data_status = pending;
2661 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2662 tasklet_schedule(&host->tasklet);
2666 spin_lock_irqsave(&host->irq_lock, irqflags);
2668 del_timer(&host->dto_timer);
2670 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2671 if (!host->data_status)
2672 host->data_status = pending;
2674 if (host->dir_status == DW_MCI_RECV_STATUS) {
2675 if (host->sg != NULL)
2676 dw_mci_read_data_pio(host, true);
2678 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2679 tasklet_schedule(&host->tasklet);
2681 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2685 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2686 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2687 dw_mci_read_data_pio(host, false);
2691 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2692 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2693 dw_mci_write_data_pio(host);
2697 spin_lock_irqsave(&host->irq_lock, irqflags);
2699 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2700 dw_mci_cmd_interrupt(host, pending);
2702 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2706 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2707 dw_mci_handle_cd(host);
2711 mci_writel(host, RINTSTS,
2719 if (host->use_dma != TRANS_MODE_IDMAC)
2723 if (host->dma_64bit_address == 1) {
2724 pending = mci_readl(host, IDSTS64);
2726 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2728 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2729 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2730 host->dma_ops->complete((void *)host);
2733 pending = mci_readl(host, IDSTS);
2735 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2737 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2738 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2739 host->dma_ops->complete((void *)host);
2748 struct dw_mci *host = slot->host;
2749 const struct dw_mci_drv_data *drv_data = host->drv_data;
2753 if (host->pdata->caps)
2754 mmc->caps = host->pdata->caps;
2756 if (host->pdata->pm_caps)
2757 mmc->pm_caps = host->pdata->pm_caps;
2759 if (host->dev->of_node) {
2760 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2764 ctrl_id = to_platform_device(host->dev)->id;
2769 dev_err(host->dev, "invalid controller id %d\n",
2776 if (host->pdata->caps2)
2777 mmc->caps2 = host->pdata->caps2;
2790 static int dw_mci_init_slot(struct dw_mci *host)
2796 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2802 slot->sdio_id = host->sdio_id0 + slot->id;
2804 slot->host = host;
2805 host->slot = slot;
2826 if (host->use_dma == TRANS_MODE_IDMAC) {
2827 mmc->max_segs = host->ring_size;
2830 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2832 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2870 slot->host->slot = NULL;
2874 static void dw_mci_init_dma(struct dw_mci *host)
2877 struct device *dev = host->dev;
2890 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2891 if (host->use_dma == DMA_INTERFACE_IDMA) {
2892 host->use_dma = TRANS_MODE_IDMAC;
2893 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2894 host->use_dma == DMA_INTERFACE_GDMA) {
2895 host->use_dma = TRANS_MODE_EDMAC;
2901 if (host->use_dma == TRANS_MODE_IDMAC) {
2906 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2909 /* host supports IDMAC in 64-bit address mode */
2910 host->dma_64bit_address = 1;
2911 dev_info(host->dev,
2913 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2914 dma_set_coherent_mask(host->dev,
2917 /* host supports IDMAC in 32-bit address mode */
2918 host->dma_64bit_address = 0;
2919 dev_info(host->dev,
2924 host->sg_cpu = dmam_alloc_coherent(host->dev,
2926 &host->sg_dma, GFP_KERNEL);
2927 if (!host->sg_cpu) {
2928 dev_err(host->dev,
2934 host->dma_ops = &dw_mci_idmac_ops;
2935 dev_info(host->dev, "Using internal DMA controller.\n");
2943 host->dma_ops = &dw_mci_edmac_ops;
2944 dev_info(host->dev, "Using external DMA controller.\n");
2947 if (host->dma_ops->init && host->dma_ops->start &&
2948 host->dma_ops->stop && host->dma_ops->cleanup) {
2949 if (host->dma_ops->init(host)) {
2950 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2955 dev_err(host->dev, "DMA initialization not found.\n");
2962 dev_info(host->dev, "Using PIO mode.\n");
2963 host->use_dma = TRANS_MODE_PIO;
2968 struct dw_mci *host = from_timer(host, t, cmd11_timer);
2970 if (host->state != STATE_SENDING_CMD11) {
2971 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2975 host->cmd_status = SDMMC_INT_RTO;
2976 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2977 tasklet_schedule(&host->tasklet);
2982 struct dw_mci *host = from_timer(host, t, cto_timer);
2986 spin_lock_irqsave(&host->irq_lock, irqflags);
2996 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2999 dev_warn(host->dev, "Unexpected interrupt latency\n");
3002 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3004 dev_warn(host->dev, "CTO timeout when already completed\n");
3012 switch (host->state) {
3021 host->cmd_status = SDMMC_INT_RTO;
3022 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3023 tasklet_schedule(&host->tasklet);
3026 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3027 host->state);
3032 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3037 struct dw_mci *host = from_timer(host, t, dto_timer);
3041 spin_lock_irqsave(&host->irq_lock, irqflags);
3047 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3050 dev_warn(host->dev, "Unexpected data interrupt latency\n");
3053 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
3055 dev_warn(host->dev, "DTO timeout when already completed\n");
3063 switch (host->state) {
3071 host->data_status = SDMMC_INT_DRTO;
3072 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3073 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3074 tasklet_schedule(&host->tasklet);
3077 dev_warn(host->dev, "Unexpected data timeout, state %d\n",
3078 host->state);
3083 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3087 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3090 struct device *dev = host->dev;
3091 const struct dw_mci_drv_data *drv_data = host->drv_data;
3113 device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3116 host->wm_aligned = true;
3122 ret = drv_data->parse_dt(host);
3131 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3137 static void dw_mci_enable_cd(struct dw_mci *host)
3146 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3149 if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3150 spin_lock_irqsave(&host->irq_lock, irqflags);
3151 temp = mci_readl(host, INTMASK);
3153 mci_writel(host, INTMASK, temp);
3154 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3158 int dw_mci_probe(struct dw_mci *host)
3160 const struct dw_mci_drv_data *drv_data = host->drv_data;
3164 if (!host->pdata) {
3165 host->pdata = dw_mci_parse_dt(host);
3166 if (IS_ERR(host->pdata))
3167 return dev_err_probe(host->dev, PTR_ERR(host->pdata),
3171 host->biu_clk = devm_clk_get(host->dev, "biu");
3172 if (IS_ERR(host->biu_clk)) {
3173 dev_dbg(host->dev, "biu clock not available\n");
3175 ret = clk_prepare_enable(host->biu_clk);
3177 dev_err(host->dev, "failed to enable biu clock\n");
3182 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3183 if (IS_ERR(host->ciu_clk)) {
3184 dev_dbg(host->dev, "ciu clock not available\n");
3185 host->bus_hz = host->pdata->bus_hz;
3187 ret = clk_prepare_enable(host->ciu_clk);
3189 dev_err(host->dev, "failed to enable ciu clock\n");
3193 if (host->pdata->bus_hz) {
3194 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3196 dev_warn(host->dev,
3198 host->pdata->bus_hz);
3200 host->bus_hz = clk_get_rate(host->ciu_clk);
3203 if (!host->bus_hz) {
3204 dev_err(host->dev,
3210 if (!IS_ERR(host->pdata->rstc)) {
3211 reset_control_assert(host->pdata->rstc);
3213 reset_control_deassert(host->pdata->rstc);
3217 ret = drv_data->init(host);
3219 dev_err(host->dev,
3225 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
3226 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
3227 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
3229 spin_lock_init(&host->lock);
3230 spin_lock_init(&host->irq_lock);
3231 INIT_LIST_HEAD(&host->queue);
3234 * Get the host data width - this assumes that HCON has been set with
3237 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3239 host->push_data = dw_mci_push_data16;
3240 host->pull_data = dw_mci_pull_data16;
3242 host->data_shift = 1;
3244 host->push_data = dw_mci_push_data64;
3245 host->pull_data = dw_mci_pull_data64;
3247 host->data_shift = 3;
3251 "HCON reports a reserved host data width!\n"
3253 host->push_data = dw_mci_push_data32;
3254 host->pull_data = dw_mci_pull_data32;
3256 host->data_shift = 2;
3260 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3265 host->dma_ops = host->pdata->dma_ops;
3266 dw_mci_init_dma(host);
3268 /* Clear the interrupts for the host controller */
3269 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3270 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3273 mci_writel(host, TMOUT, 0xFFFFFFFF);
3279 if (!host->pdata->fifo_depth) {
3286 fifo_size = mci_readl(host, FIFOTH);
3289 fifo_size = host->pdata->fifo_depth;
3291 host->fifo_depth = fifo_size;
3292 host->fifoth_val =
3294 mci_writel(host, FIFOTH, host->fifoth_val);
3297 mci_writel(host, CLKENA, 0);
3298 mci_writel(host, CLKSRC, 0);
3304 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3305 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3307 if (host->data_addr_override)
3308 host->fifo_reg = host->regs + host->data_addr_override;
3309 else if (host->verid < DW_MMC_240A)
3310 host->fifo_reg = host->regs + DATA_OFFSET;
3312 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3314 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3315 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3316 host->irq_flags, "dw-mci", host);
3324 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3328 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3330 dev_info(host->dev,
3331 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3332 host->irq, width, fifo_size);
3335 ret = dw_mci_init_slot(host);
3337 dev_dbg(host->dev, "slot %d init failed\n", i);
3342 dw_mci_enable_cd(host);
3347 if (host->use_dma && host->dma_ops->exit)
3348 host->dma_ops->exit(host);
3350 if (!IS_ERR(host->pdata->rstc))
3351 reset_control_assert(host->pdata->rstc);
3354 clk_disable_unprepare(host->ciu_clk);
3357 clk_disable_unprepare(host->biu_clk);
3363 void dw_mci_remove(struct dw_mci *host)
3365 dev_dbg(host->dev, "remove slot\n");
3366 if (host->slot)
3367 dw_mci_cleanup_slot(host->slot);
3369 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3370 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3373 mci_writel(host, CLKENA, 0);
3374 mci_writel(host, CLKSRC, 0);
3376 if (host->use_dma && host->dma_ops->exit)
3377 host->dma_ops->exit(host);
3379 if (!IS_ERR(host->pdata->rstc))
3380 reset_control_assert(host->pdata->rstc);
3382 clk_disable_unprepare(host->ciu_clk);
3383 clk_disable_unprepare(host->biu_clk);
3392 struct dw_mci *host = dev_get_drvdata(dev);
3394 if (host->use_dma && host->dma_ops->exit)
3395 host->dma_ops->exit(host);
3397 clk_disable_unprepare(host->ciu_clk);
3399 if (host->slot &&
3400 (mmc_can_gpio_cd(host->slot->mmc) ||
3401 !mmc_card_is_removable(host->slot->mmc)))
3402 clk_disable_unprepare(host->biu_clk);
3411 struct dw_mci *host = dev_get_drvdata(dev);
3413 if (host->slot &&
3414 (mmc_can_gpio_cd(host->slot->mmc) ||
3415 !mmc_card_is_removable(host->slot->mmc))) {
3416 ret = clk_prepare_enable(host->biu_clk);
3421 ret = clk_prepare_enable(host->ciu_clk);
3425 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3426 clk_disable_unprepare(host->ciu_clk);
3431 if (host->use_dma && host->dma_ops->init)
3432 host->dma_ops->init(host);
3438 mci_writel(host, FIFOTH, host->fifoth_val);
3439 host->prev_blksz = 0;
3442 mci_writel(host, TMOUT, 0xFFFFFFFF);
3444 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3445 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3448 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3451 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3452 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3455 dw_mci_setup_bus(host->slot, true);
3458 if (sdio_irq_claimed(host->slot->mmc))
3459 __dw_mci_enable_sdio_irq(host->slot, 1);
3462 dw_mci_enable_cd(host);
3467 if (host->slot &&
3468 (mmc_can_gpio_cd(host->slot->mmc) ||
3469 !mmc_card_is_removable(host->slot->mmc)))
3470 clk_disable_unprepare(host->biu_clk);