Lines Matching defs:clock
277 * We need to disable low power mode (automatic clock stop)
279 * since stopping the clock is a specific part of the UHS
284 * ever called with a non-zero clock. That shouldn't happen
1202 unsigned int clock = slot->clock;
1213 if (!clock) {
1216 } else if (clock != host->current_speed || force_clkinit) {
1217 div = host->bus_hz / clock;
1218 if (host->bus_hz % clock && host->bus_hz > clock)
1225 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1227 if ((clock != slot->__clk_old &&
1234 slot->id, host->bus_hz, clock,
1243 slot->mmc->f_min == clock)
1247 /* disable clock */
1254 /* set clock to desired speed */
1260 /* enable clock; only low power if no SDIO */
1269 /* keep the last clock value that was requested from core */
1270 slot->__clk_old = clock;
1275 host->current_speed = clock;
1308 /* this is the first command, send the initialization clock */
1439 * Use mirror of ios->clock to prevent race with mmc
1442 slot->clock = ios->clock;
1484 /* Adjust clock / bus width after power is up */
1489 /* Turn clock off before power goes down */
1507 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1615 * Low power mode will stop the card clock when idle. According to the
1753 /* if the controller reset bit did clear, then set clock regs */
1756 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1769 /* After a CTRL reset we need to have CIU set clock registers */
3118 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3173 dev_dbg(host->dev, "biu clock not available\n");
3177 dev_err(host->dev, "failed to enable biu clock\n");
3184 dev_dbg(host->dev, "ciu clock not available\n");
3189 dev_err(host->dev, "failed to enable ciu clock\n");
3296 /* disable clock to CIU */
3372 /* disable clock to CIU */
3454 /* Force setup bus to guarantee available clock output */