Lines Matching refs:phase
68 * Set the drive phase offset based on speed mode to achieve hold times.
94 int phase;
97 * In almost all cases a 90 degree phase offset will provide
102 phase = 90;
108 * bus width is 8 we need to double the phase offset
112 phase = 180;
124 phase = 180;
128 clk_set_phase(priv->drv_clk, phase);
163 /* Try each phase and extract good ranges */
213 dev_info(host->dev, "All phases work, using default phase %d.",
230 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
239 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
249 dev_info(host->dev, "Successfully tuned phase to %d\n",
274 if (of_property_read_u32(np, "rockchip,default-sample-phase",