Lines Matching refs:smpl_phase
217 int smpl_phase)
232 if (smpl_phase == -1)
233 smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
238 if (smpl_phase >= USE_DLY_MIN_SMPL &&
239 smpl_phase <= USE_DLY_MAX_SMPL)
243 if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL &&
244 smpl_phase <= ENABLE_SHIFT_MAX_SMPL)
252 reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) |
372 int smpl_phase = 0;
376 for (i = 0; i < NUM_PHASES; ++i, ++smpl_phase) {
377 smpl_phase %= 32;
380 dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase);
383 tuning_sample_flag |= (1 << smpl_phase);
385 tuning_sample_flag &= ~(1 << smpl_phase);