Lines Matching defs:host
16 #include <linux/mmc/host.h>
217 static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host)
219 host->buffer_bytes_left = sg_dma_len(host->sg);
220 host->buffer = sg_virt(host->sg);
221 if (host->buffer_bytes_left > host->bytes_left)
222 host->buffer_bytes_left = host->bytes_left;
225 static void davinci_fifo_data_trans(struct mmc_davinci_host *host,
231 if (host->buffer_bytes_left == 0) {
232 host->sg = sg_next(host->data->sg);
233 mmc_davinci_sg_to_buf(host);
236 p = host->buffer;
237 if (n > host->buffer_bytes_left)
238 n = host->buffer_bytes_left;
239 host->buffer_bytes_left -= n;
240 host->bytes_left -= n;
246 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
248 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR);
252 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3));
257 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR);
261 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3));
265 host->buffer = p;
268 static void mmc_davinci_start_command(struct mmc_davinci_host *host,
274 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n",
294 host->cmd = cmd;
315 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n",
324 if (host->do_dma)
327 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL &&
328 host->data_dir == DAVINCI_MMC_DATADIR_READ)
336 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
339 if (host->bus_mode == MMC_BUSMODE_PUSHPULL)
343 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
347 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
350 if (!host->do_dma)
352 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
355 if (!host->do_dma)
363 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE))
364 davinci_fifo_data_trans(host, rw_threshold);
366 writel(cmd->arg, host->base + DAVINCI_MMCARGHL);
367 writel(cmd_reg, host->base + DAVINCI_MMCCMD);
369 host->active_request = true;
371 if (!host->do_dma && host->bytes_left <= poll_threshold) {
374 while (host->active_request && count--) {
375 mmc_davinci_irq(0, host);
380 if (host->active_request)
381 writel(im_val, host->base + DAVINCI_MMCIM);
388 static void davinci_abort_dma(struct mmc_davinci_host *host)
392 if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
393 sync_dev = host->dma_rx;
395 sync_dev = host->dma_tx;
400 static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
407 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
410 .dst_addr = host->mem_res->start + DAVINCI_MMCDXR,
415 chan = host->dma_tx;
416 dmaengine_slave_config(host->dma_tx, &dma_tx_conf);
418 desc = dmaengine_prep_slave_sg(host->dma_tx,
420 host->sg_len,
424 dev_dbg(mmc_dev(host->mmc),
432 .src_addr = host->mem_res->start + DAVINCI_MMCDRR,
437 chan = host->dma_rx;
438 dmaengine_slave_config(host->dma_rx, &dma_rx_conf);
440 desc = dmaengine_prep_slave_sg(host->dma_rx,
442 host->sg_len,
446 dev_dbg(mmc_dev(host->mmc),
460 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
467 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
471 for (i = 0; i < host->sg_len; i++) {
473 dma_unmap_sg(mmc_dev(host->mmc),
480 host->do_dma = 1;
481 ret = mmc_davinci_send_dma_request(host, data);
486 static void davinci_release_dma_channels(struct mmc_davinci_host *host)
488 if (!host->use_dma)
491 dma_release_channel(host->dma_tx);
492 dma_release_channel(host->dma_rx);
495 static int davinci_acquire_dma_channels(struct mmc_davinci_host *host)
497 host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx");
498 if (IS_ERR(host->dma_tx)) {
499 dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n");
500 return PTR_ERR(host->dma_tx);
503 host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx");
504 if (IS_ERR(host->dma_rx)) {
505 dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n");
506 dma_release_channel(host->dma_tx);
507 return PTR_ERR(host->dma_rx);
516 mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req)
522 if (host->version == MMC_CTLR_VERSION_2)
525 host->data = data;
527 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
528 writel(0, host->base + DAVINCI_MMCBLEN);
529 writel(0, host->base + DAVINCI_MMCNBLK);
533 dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n",
536 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n",
539 (data->timeout_ns / host->ns_in_one_cycle);
543 writel(timeout, host->base + DAVINCI_MMCTOD);
544 writel(data->blocks, host->base + DAVINCI_MMCNBLK);
545 writel(data->blksz, host->base + DAVINCI_MMCBLEN);
549 host->data_dir = DAVINCI_MMC_DATADIR_WRITE;
551 host->base + DAVINCI_MMCFIFOCTL);
553 host->base + DAVINCI_MMCFIFOCTL);
555 host->data_dir = DAVINCI_MMC_DATADIR_READ;
557 host->base + DAVINCI_MMCFIFOCTL);
559 host->base + DAVINCI_MMCFIFOCTL);
562 host->buffer = NULL;
563 host->bytes_left = data->blocks * data->blksz;
573 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0
574 && mmc_davinci_start_dma_transfer(host, data) == 0) {
576 host->bytes_left = 0;
579 host->sg_len = data->sg_len;
580 host->sg = host->data->sg;
581 mmc_davinci_sg_to_buf(host);
587 struct mmc_davinci_host *host = mmc_priv(mmc);
595 mmcst1 = readl(host->base + DAVINCI_MMCST1);
601 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n");
607 host->do_dma = 0;
608 mmc_davinci_prepare_data(host, req);
609 mmc_davinci_start_command(host, req->cmd);
612 static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host,
617 mmc_pclk = host->mmc_input_clk;
631 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
634 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
644 struct mmc_davinci_host *host = mmc_priv(mmc);
658 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
660 writel(temp, host->base + DAVINCI_MMCCLK);
663 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000);
666 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock);
671 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
672 writel(temp, host->base + DAVINCI_MMCCLK);
676 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
678 writel(temp, host->base + DAVINCI_MMCCLK);
680 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
688 struct mmc_davinci_host *host = mmc_priv(mmc);
692 dev_dbg(mmc_dev(host->mmc),
710 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n");
711 writel((readl(host->base + DAVINCI_MMCCTL) &
713 host->base + DAVINCI_MMCCTL);
716 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n");
717 if (host->version == MMC_CTLR_VERSION_2)
718 writel((readl(host->base + DAVINCI_MMCCTL) &
720 host->base + DAVINCI_MMCCTL);
722 writel(readl(host->base + DAVINCI_MMCCTL) |
724 host->base + DAVINCI_MMCCTL);
727 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n");
728 if (host->version == MMC_CTLR_VERSION_2)
729 writel(readl(host->base + DAVINCI_MMCCTL) &
731 host->base + DAVINCI_MMCCTL);
733 writel(readl(host->base + DAVINCI_MMCCTL) &
735 host->base + DAVINCI_MMCCTL);
741 host->bus_mode = ios->bus_mode;
747 writel(0, host->base + DAVINCI_MMCARGHL);
748 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD);
750 u32 tmp = readl(host->base + DAVINCI_MMCST0);
759 dev_warn(mmc_dev(host->mmc), "powerup timeout\n");
766 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
768 host->data = NULL;
770 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) {
776 if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) &
778 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
779 mmc_signal_sdio_irq(host->mmc);
783 if (host->do_dma) {
784 davinci_abort_dma(host);
786 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
788 host->do_dma = false;
790 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
792 if (!data->stop || (host->cmd && host->cmd->error)) {
793 mmc_request_done(host->mmc, data->mrq);
794 writel(0, host->base + DAVINCI_MMCIM);
795 host->active_request = false;
797 mmc_davinci_start_command(host, data->stop);
800 static void mmc_davinci_cmd_done(struct mmc_davinci_host *host,
803 host->cmd = NULL;
808 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01);
809 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23);
810 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45);
811 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
814 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
818 if (host->data == NULL || cmd->error) {
821 mmc_request_done(host->mmc, cmd->mrq);
822 writel(0, host->base + DAVINCI_MMCIM);
823 host->active_request = false;
827 static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host,
832 temp = readl(host->base + DAVINCI_MMCCTL);
838 writel(temp, host->base + DAVINCI_MMCCTL);
843 davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
845 mmc_davinci_reset_ctrl(host, 1);
846 mmc_davinci_reset_ctrl(host, 0);
851 struct mmc_davinci_host *host = dev_id;
854 status = readl(host->base + DAVINCI_SDIOIST);
856 dev_dbg(mmc_dev(host->mmc),
858 writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
859 mmc_signal_sdio_irq(host->mmc);
866 struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
870 struct mmc_data *data = host->data;
872 if (host->cmd == NULL && host->data == NULL) {
873 status = readl(host->base + DAVINCI_MMCST0);
874 dev_dbg(mmc_dev(host->mmc),
877 writel(0, host->base + DAVINCI_MMCIM);
881 status = readl(host->base + DAVINCI_MMCST0);
891 if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) {
901 im_val = readl(host->base + DAVINCI_MMCIM);
902 writel(0, host->base + DAVINCI_MMCIM);
905 davinci_fifo_data_trans(host, rw_threshold);
906 status = readl(host->base + DAVINCI_MMCST0);
908 } while (host->bytes_left &&
917 writel(im_val, host->base + DAVINCI_MMCIM);
923 if ((host->do_dma == 0) && (host->bytes_left > 0)) {
927 davinci_fifo_data_trans(host, host->bytes_left);
932 dev_err(mmc_dev(host->mmc),
933 "DATDNE with no host->data\n");
942 dev_dbg(mmc_dev(host->mmc),
946 davinci_abort_data(host, data);
961 u32 temp = readb(host->base + DAVINCI_MMCDRSP);
966 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n",
970 davinci_abort_data(host, data);
975 if (host->cmd) {
976 dev_dbg(mmc_dev(host->mmc),
978 host->cmd->opcode, qstatus);
979 host->cmd->error = -ETIMEDOUT;
982 davinci_abort_data(host, data);
990 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n");
991 if (host->cmd) {
992 host->cmd->error = -EILSEQ;
999 end_command = host->cmd ? 1 : 0;
1003 mmc_davinci_cmd_done(host, host->cmd);
1005 mmc_davinci_xfer_done(host, data);
1033 struct mmc_davinci_host *host = mmc_priv(mmc);
1036 if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) {
1037 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
1038 mmc_signal_sdio_irq(host->mmc);
1040 host->sdio_int = true;
1041 writel(readl(host->base + DAVINCI_SDIOIEN) |
1042 SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN);
1045 host->sdio_int = false;
1046 writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
1047 host->base + DAVINCI_SDIOIEN);
1065 struct mmc_davinci_host *host;
1070 host = container_of(nb, struct mmc_davinci_host, freq_transition);
1071 mmc = host->mmc;
1072 mmc_pclk = clk_get_rate(host->clk);
1076 host->mmc_input_clk = mmc_pclk;
1084 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1086 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition;
1088 return cpufreq_register_notifier(&host->freq_transition,
1092 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1094 cpufreq_unregister_notifier(&host->freq_transition,
1098 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1103 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1107 static void init_mmcsd_host(struct mmc_davinci_host *host)
1110 mmc_davinci_reset_ctrl(host, 1);
1112 writel(0, host->base + DAVINCI_MMCCLK);
1113 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
1115 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
1116 writel(0xFFFF, host->base + DAVINCI_MMCTOD);
1118 mmc_davinci_reset_ctrl(host, 0);
1150 struct mmc_davinci_host *host;
1156 host = mmc_priv(mmc);
1157 if (!host)
1161 host->nr_sg = pdata->nr_sg - 1;
1193 struct mmc_davinci_host *host = NULL;
1217 host = mmc_priv(mmc);
1218 host->mmc = mmc; /* Important */
1220 host->mem_res = mem;
1221 host->base = devm_ioremap(&pdev->dev, mem->start, mem_size);
1222 if (!host->base) {
1227 host->clk = devm_clk_get(&pdev->dev, NULL);
1228 if (IS_ERR(host->clk)) {
1229 ret = PTR_ERR(host->clk);
1232 ret = clk_prepare_enable(host->clk);
1236 host->mmc_input_clk = clk_get_rate(host->clk);
1255 if (host->nr_sg > MAX_NR_SG || !host->nr_sg)
1256 host->nr_sg = MAX_NR_SG;
1258 init_mmcsd_host(host);
1260 host->use_dma = use_dma;
1261 host->mmc_irq = irq;
1262 host->sdio_irq = platform_get_irq(pdev, 1);
1264 if (host->use_dma) {
1265 ret = davinci_acquire_dma_channels(host);
1269 host->use_dma = 0;
1276 host->version = id_entry->driver_data;
1295 dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs);
1296 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size);
1297 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size);
1298 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size);
1300 platform_set_drvdata(pdev, host);
1302 ret = mmc_davinci_cpufreq_register(host);
1313 mmc_hostname(mmc), host);
1317 if (host->sdio_irq >= 0) {
1318 ret = devm_request_irq(&pdev->dev, host->sdio_irq,
1320 mmc_hostname(mmc), host);
1327 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
1328 host->use_dma ? "DMA" : "PIO",
1336 mmc_davinci_cpufreq_deregister(host);
1338 davinci_release_dma_channels(host);
1341 clk_disable_unprepare(host->clk);
1352 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1354 mmc_remove_host(host->mmc);
1355 mmc_davinci_cpufreq_deregister(host);
1356 davinci_release_dma_channels(host);
1357 clk_disable_unprepare(host->clk);
1358 mmc_free_host(host->mmc);
1366 struct mmc_davinci_host *host = dev_get_drvdata(dev);
1368 writel(0, host->base + DAVINCI_MMCIM);
1369 mmc_davinci_reset_ctrl(host, 1);
1370 clk_disable(host->clk);
1377 struct mmc_davinci_host *host = dev_get_drvdata(dev);
1380 ret = clk_enable(host->clk);
1384 mmc_davinci_reset_ctrl(host, 0);