Lines Matching defs:DAVINCI_MMCCLK
34 #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */
78 /* DAVINCI_MMCCLK definitions */
658 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
660 writel(temp, host->base + DAVINCI_MMCCLK);
671 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
672 writel(temp, host->base + DAVINCI_MMCCLK);
676 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
678 writel(temp, host->base + DAVINCI_MMCCLK);
680 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
1112 writel(0, host->base + DAVINCI_MMCCLK);
1113 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);