Lines Matching refs:cch
545 struct gru_context_configuration_handle *cch;
550 cch = get_cch(gru->gs_gru_base_vaddr, ctxnum);
554 lock_cch_handle(cch);
555 if (cch_interrupt_sync(cch))
567 if (cch_deallocate(cch))
569 unlock_cch_handle(cch);
581 struct gru_context_configuration_handle *cch;
584 cch = get_cch(gru->gs_gru_base_vaddr, ctxnum);
585 lock_cch_handle(cch);
586 cch->tfm_fault_bit_enable =
589 cch->tlb_int_enable = (gts->ts_user_options == GRU_OPT_MISS_FMM_INTR);
590 if (cch->tlb_int_enable) {
592 cch->tlb_int_select = gts->ts_tlb_int_select;
595 cch->req_slice_set_enable = 1;
596 cch->req_slice = gts->ts_cch_req_slice;
598 cch->req_slice_set_enable =0;
600 cch->tfm_done_bit_enable = 0;
601 cch->dsr_allocation_map = gts->ts_dsr_map;
602 cch->cbr_allocation_map = gts->ts_cbr_map;
605 cch->unmap_enable = 1;
606 cch->tfm_done_bit_enable = 1;
607 cch->cb_int_enable = 1;
608 cch->tlb_int_select = 0; /* For now, ints go to cpu 0 */
610 cch->unmap_enable = 0;
611 cch->tfm_done_bit_enable = 0;
612 cch->cb_int_enable = 0;
615 cch->asid[i] = asid + i;
616 cch->sizeavail[i] = gts->ts_sizeavail;
620 err = cch_allocate(cch);
623 "err %d: cch %p, gts %p, cbr 0x%lx, dsr 0x%lx\n",
624 err, cch, gts, gts->ts_cbr_map, gts->ts_dsr_map);
631 if (cch_start(cch))
633 unlock_cch_handle(cch);
647 struct gru_context_configuration_handle *cch;
651 cch = get_cch(gru->gs_gru_base_vaddr, ctxnum);
653 lock_cch_handle(cch);
654 if (cch->state == CCHSTATE_ACTIVE) {
657 if (cch_interrupt(cch))
660 cch->sizeavail[i] = gts->ts_sizeavail;
662 cch->tlb_int_select = gru_cpu_fault_map_id();
663 cch->tfm_fault_bit_enable =
666 if (cch_start(cch))
671 unlock_cch_handle(cch);