Lines Matching refs:caddr
32 #define PHN_IRQCTL 0x4c /* irq control in caddr space */
43 void __iomem *caddr;
69 iowrite32(0x43, dev->caddr + PHN_IRQCTL);
70 ioread32(dev->caddr + PHN_IRQCTL); /* PCI posting */
72 iowrite32(0, dev->caddr + PHN_IRQCTL);
73 ioread32(dev->caddr + PHN_IRQCTL); /* PCI posting */
369 pht->caddr = pci_iomap(pdev, 0, 0);
370 if (pht->caddr == NULL) {
391 iowrite32(0, pht->caddr + PHN_IRQCTL);
392 ioread32(pht->caddr + PHN_IRQCTL); /* PCI posting */
421 pci_iounmap(pdev, pht->caddr);
443 iowrite32(0, pht->caddr + PHN_IRQCTL);
444 ioread32(pht->caddr + PHN_IRQCTL); /* PCI posting */
449 pci_iounmap(pdev, pht->caddr);
464 iowrite32(0, dev->caddr + PHN_IRQCTL);
465 ioread32(dev->caddr + PHN_IRQCTL); /* PCI posting */
476 iowrite32(0, dev->caddr + PHN_IRQCTL);