Lines Matching refs:chip
138 * @chip: Pointer to the PHUB register structure
143 static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
147 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
155 struct pch_phub_reg *chip = pci_get_drvdata(pdev);
157 void __iomem *p = chip->pch_phub_base_address;
159 chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
160 chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
161 chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
162 chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
163 chip->comp_resp_timeout_reg =
165 chip->bus_slave_control_reg =
167 chip->deadlock_avoid_type_reg =
169 chip->intpin_reg_wpermit_reg0 =
171 chip->intpin_reg_wpermit_reg1 =
173 chip->intpin_reg_wpermit_reg2 =
175 chip->intpin_reg_wpermit_reg3 =
178 "chip->phub_id_reg=%x, "
179 "chip->q_pri_val_reg=%x, "
180 "chip->rc_q_maxsize_reg=%x, "
181 "chip->bri_q_maxsize_reg=%x, "
182 "chip->comp_resp_timeout_reg=%x, "
183 "chip->bus_slave_control_reg=%x, "
184 "chip->deadlock_avoid_type_reg=%x, "
185 "chip->intpin_reg_wpermit_reg0=%x, "
186 "chip->intpin_reg_wpermit_reg1=%x, "
187 "chip->intpin_reg_wpermit_reg2=%x, "
188 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
189 chip->phub_id_reg,
190 chip->q_pri_val_reg,
191 chip->rc_q_maxsize_reg,
192 chip->bri_q_maxsize_reg,
193 chip->comp_resp_timeout_reg,
194 chip->bus_slave_control_reg,
195 chip->deadlock_avoid_type_reg,
196 chip->intpin_reg_wpermit_reg0,
197 chip->intpin_reg_wpermit_reg1,
198 chip->intpin_reg_wpermit_reg2,
199 chip->intpin_reg_wpermit_reg3);
201 chip->int_reduce_control_reg[i] =
204 "chip->int_reduce_control_reg[%d]=%x\n",
205 __func__, i, chip->int_reduce_control_reg[i]);
207 chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
208 if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
209 chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
216 struct pch_phub_reg *chip = pci_get_drvdata(pdev);
218 p = chip->pch_phub_base_address;
220 iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
221 iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
222 iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
223 iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
224 iowrite32(chip->comp_resp_timeout_reg,
226 iowrite32(chip->bus_slave_control_reg,
228 iowrite32(chip->deadlock_avoid_type_reg,
230 iowrite32(chip->intpin_reg_wpermit_reg0,
232 iowrite32(chip->intpin_reg_wpermit_reg1,
234 iowrite32(chip->intpin_reg_wpermit_reg2,
236 iowrite32(chip->intpin_reg_wpermit_reg3,
239 "chip->phub_id_reg=%x, "
240 "chip->q_pri_val_reg=%x, "
241 "chip->rc_q_maxsize_reg=%x, "
242 "chip->bri_q_maxsize_reg=%x, "
243 "chip->comp_resp_timeout_reg=%x, "
244 "chip->bus_slave_control_reg=%x, "
245 "chip->deadlock_avoid_type_reg=%x, "
246 "chip->intpin_reg_wpermit_reg0=%x, "
247 "chip->intpin_reg_wpermit_reg1=%x, "
248 "chip->intpin_reg_wpermit_reg2=%x, "
249 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
250 chip->phub_id_reg,
251 chip->q_pri_val_reg,
252 chip->rc_q_maxsize_reg,
253 chip->bri_q_maxsize_reg,
254 chip->comp_resp_timeout_reg,
255 chip->bus_slave_control_reg,
256 chip->deadlock_avoid_type_reg,
257 chip->intpin_reg_wpermit_reg0,
258 chip->intpin_reg_wpermit_reg1,
259 chip->intpin_reg_wpermit_reg2,
260 chip->intpin_reg_wpermit_reg3);
262 iowrite32(chip->int_reduce_control_reg[i],
265 "chip->int_reduce_control_reg[%d]=%x\n",
266 __func__, i, chip->int_reduce_control_reg[i]);
269 iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
270 if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
271 iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
276 * @chip: Pointer to the PHUB register structure
280 static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
283 void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
291 * @chip: Pointer to the PHUB register structure
295 static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
298 void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
308 chip->pch_phub_extrom_base_address + PHUB_CONTROL);
314 while (ioread8(chip->pch_phub_extrom_base_address +
323 chip->pch_phub_extrom_base_address + PHUB_CONTROL);
330 * @chip: Pointer to the PHUB register structure
334 static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
339 mem_addr = chip->pch_mac_start_address +
342 pch_phub_read_serial_rom(chip, mem_addr, data);
347 * @chip: Pointer to the PHUB register structure
351 static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
357 mem_addr = chip->pch_mac_start_address +
360 retval = pch_phub_write_serial_rom(chip, mem_addr, data);
368 static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
372 retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
373 retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
374 retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
375 retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
377 retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
378 retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
379 retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
380 retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
382 retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
383 retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
384 retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
385 retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
387 retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
388 retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
389 retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
390 retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
392 retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
393 retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
394 retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
395 retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
397 retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
398 retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
399 retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
400 retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
408 static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
414 retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
415 retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
416 retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
417 retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
419 retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
420 retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
421 retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
422 retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
424 retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
425 retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
426 retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
427 retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
429 retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
430 retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
431 retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
432 retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
434 retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
435 retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
436 retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
437 retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
439 retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
440 retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
441 retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
442 retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
449 * @chip: Pointer to the PHUB register structure
452 static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
456 pch_phub_read_serial_rom_val(chip, i, &data[i]);
461 * @chip: Pointer to the PHUB register structure
464 static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
469 if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/
470 retval = pch_phub_gbe_serial_rom_conf(chip);
472 retval = pch_phub_gbe_serial_rom_conf_mp(chip);
477 retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
498 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
507 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
508 if (!chip->pch_phub_extrom_base_address) {
513 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
516 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
520 pch_phub_read_serial_rom(chip,
521 chip->pch_opt_rom_start_address + 2,
534 pch_phub_read_serial_rom(chip,
535 chip->pch_opt_rom_start_address + addr_offset + off,
543 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
548 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
563 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
578 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
579 if (!chip->pch_phub_extrom_base_address) {
588 ret = pch_phub_write_serial_rom(chip,
589 chip->pch_opt_rom_start_address + addr_offset + off,
598 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
603 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
614 struct pch_phub_reg *chip = dev_get_drvdata(dev);
617 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
618 if (!chip->pch_phub_extrom_base_address)
621 pch_phub_read_gbe_mac_addr(chip, mac);
622 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
632 struct pch_phub_reg *chip = dev_get_drvdata(dev);
638 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
639 if (!chip->pch_phub_extrom_base_address)
642 ret = pch_phub_write_gbe_mac_addr(chip, mac);
643 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
666 struct pch_phub_reg *chip;
668 chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL);
669 if (chip == NULL)
690 chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
693 if (chip->pch_phub_base_address == NULL) {
700 chip->pch_phub_base_address);
702 chip->pdev = pdev; /* Save pci device struct */
722 pch_phub_read_modify_write_reg(chip,
730 pch_phub_read_modify_write_reg(chip,
737 iowrite32(prefetch, chip->pch_phub_base_address + 0x14);
739 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
740 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
741 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
746 pch_phub_read_modify_write_reg(chip,
762 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
763 chip->pch_opt_rom_start_address =\
769 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
771 iowrite32(0x25, chip->pch_phub_base_address + 0x140);
772 chip->pch_opt_rom_start_address =\
774 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
788 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
789 chip->pch_opt_rom_start_address =\
791 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
803 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
805 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
806 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
807 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
810 chip->ioh_type = id->driver_data;
811 pci_set_drvdata(pdev, chip);
818 pci_iounmap(pdev, chip->pch_phub_base_address);
824 kfree(chip);
831 struct pch_phub_reg *chip = pci_get_drvdata(pdev);
835 pci_iounmap(pdev, chip->pch_phub_base_address);
838 kfree(chip);