Lines Matching refs:val

8 #define EXTRACT_BIT(val, bit) (!!(val & BIT(bit)))
9 #define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)
90 u16 val;
103 pci_read_config_word(dev, pos + PCI_PASID_CAP, &val);
104 fn->max_pasid_log = EXTRACT_BITS(val, 8, 12);
131 u32 val;
140 pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
141 afu_present = EXTRACT_BIT(val, 31);
147 fn->max_afu_index = EXTRACT_BITS(val, 24, 29);
241 int ocxl_config_get_reset_reload(struct pci_dev *dev, int *val)
253 *val = !!(reset_reload & BIT(0));
257 int ocxl_config_set_reset_reload(struct pci_dev *dev, int val)
268 if (val)
338 u32 val;
349 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
350 while (!EXTRACT_BIT(val, 31)) {
358 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
437 u32 val, *ptr;
441 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val);
445 *ptr = le32_to_cpu((__force __le32) val);
455 u32 val;
460 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val);
463 afu->global_mmio_bar = EXTRACT_BITS(val, 0, 2);
464 afu->global_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
466 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val);
469 afu->global_mmio_offset += (u64) val << 32;
471 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val);
474 afu->global_mmio_size = val;
479 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val);
482 afu->pp_mmio_bar = EXTRACT_BITS(val, 0, 2);
483 afu->pp_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
485 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val);
488 afu->pp_mmio_offset += (u64) val << 32;
490 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val);
493 afu->pp_mmio_stride = val;
753 u16 val;
755 val = actag_count & OCXL_DVSEC_ACTAG_MASK;
756 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val);
758 val = actag_base & OCXL_DVSEC_ACTAG_MASK;
759 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
788 u8 val;
790 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val);
792 val |= 1;
794 val &= 0xFE;
795 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
801 u32 val;
846 val = recv_cap >> 32;
847 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val);
848 val = recv_cap & GENMASK(31, 0);
849 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val);
857 &val);
859 *be32ptr = cpu_to_be32(val);
861 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val);
862 recv_cap = (long) val << 32;
863 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val);
864 recv_cap |= val;
900 u32 val;
904 &val);
905 if (EXTRACT_BIT(val, 20)) {
912 val &= ~OCXL_DVSEC_PASID_MASK;
913 val |= pasid & OCXL_DVSEC_PASID_MASK;
914 val |= BIT(20);
917 val);
921 &val);
922 while (EXTRACT_BIT(val, 20)) {
932 &val);
941 u32 val;
943 val = (tag_first & OCXL_DVSEC_ACTAG_MASK) << 16;
944 val |= tag_count & OCXL_DVSEC_ACTAG_MASK;
946 val);