Lines Matching refs:dev
34 static int find_dvsec(struct pci_dev *dev, int dvsec_id)
39 while ((vsec = pci_find_next_ext_capability(dev, vsec,
41 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
43 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
50 static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)
56 while ((vsec = pci_find_next_ext_capability(dev, vsec,
58 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
60 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
64 pci_read_config_byte(dev,
80 static struct pci_dev *get_function_0(struct pci_dev *dev)
82 unsigned int devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
84 return pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus),
85 dev->bus->number, devfn);
88 static void read_pasid(struct pci_dev *dev, struct ocxl_fn_config *fn)
93 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PASID);
99 dev_dbg(&dev->dev, "Function doesn't require any PASID\n");
103 pci_read_config_word(dev, pos + PCI_PASID_CAP, &val);
107 dev_dbg(&dev->dev, "PASID capability:\n");
108 dev_dbg(&dev->dev, " Max PASID log = %d\n", fn->max_pasid_log);
111 static int read_dvsec_tl(struct pci_dev *dev, struct ocxl_fn_config *fn)
115 pos = find_dvsec(dev, OCXL_DVSEC_TL_ID);
116 if (!pos && PCI_FUNC(dev->devfn) == 0) {
117 dev_err(&dev->dev, "Can't find TL DVSEC\n");
120 if (pos && PCI_FUNC(dev->devfn) != 0) {
121 dev_err(&dev->dev, "TL DVSEC is only allowed on function 0\n");
128 static int read_dvsec_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
133 pos = find_dvsec(dev, OCXL_DVSEC_FUNC_ID);
135 dev_err(&dev->dev, "Can't find function DVSEC\n");
140 pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
144 dev_dbg(&dev->dev, "Function doesn't define any AFU\n");
150 dev_dbg(&dev->dev, "Function DVSEC:\n");
151 dev_dbg(&dev->dev, " Max AFU index = %d\n", fn->max_afu_index);
155 static int read_dvsec_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn)
164 pos = find_dvsec(dev, OCXL_DVSEC_AFU_INFO_ID);
166 dev_err(&dev->dev, "Can't find AFU information DVSEC\n");
173 static int read_dvsec_vendor(struct pci_dev *dev)
186 if (PCI_FUNC(dev->devfn) != 0)
189 pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
193 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_CFG_VERS, &cfg);
194 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_TLX_VERS, &tlx);
195 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_DLX_VERS, &dlx);
196 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
199 dev_dbg(&dev->dev, "Vendor specific DVSEC:\n");
200 dev_dbg(&dev->dev, " CFG version = 0x%x\n", cfg);
201 dev_dbg(&dev->dev, " TLX version = 0x%x\n", tlx);
202 dev_dbg(&dev->dev, " DLX version = 0x%x\n", dlx);
203 dev_dbg(&dev->dev, " ResetReload = 0x%x\n", reset_reload);
209 * @dev: PCI device to match
219 static int get_dvsec_vendor0(struct pci_dev *dev, struct pci_dev **dev0,
224 if (PCI_FUNC(dev->devfn) != 0) {
225 dev = get_function_0(dev);
226 if (!dev)
229 dev = pci_dev_get(dev);
231 pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
233 pci_dev_put(dev);
236 *dev0 = dev;
241 int ocxl_config_get_reset_reload(struct pci_dev *dev, int *val)
247 if (get_dvsec_vendor0(dev, &dev0, &pos))
257 int ocxl_config_set_reset_reload(struct pci_dev *dev, int val)
263 if (get_dvsec_vendor0(dev, &dev0, &pos))
278 static int validate_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
281 dev_err(&dev->dev,
287 dev_err(&dev->dev,
295 int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
299 read_pasid(dev, fn);
301 rc = read_dvsec_tl(dev, fn);
303 dev_err(&dev->dev,
309 rc = read_dvsec_function(dev, fn);
311 dev_err(&dev->dev,
316 rc = read_dvsec_afu_info(dev, fn);
318 dev_err(&dev->dev, "Invalid AFU configuration: %d\n", rc);
322 rc = read_dvsec_vendor(dev);
324 dev_err(&dev->dev,
330 rc = validate_function(dev, fn);
335 static int read_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn,
344 dev_err(&dev->dev, "Invalid offset in AFU info DVSEC\n");
348 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, offset);
349 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
352 dev_err(&dev->dev,
358 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
360 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_DATA, data);
366 * @dev: the device for the AFU
373 static int read_template_version(struct pci_dev *dev, struct ocxl_fn_config *fn,
380 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_VERSION, &val32);
391 int ocxl_config_check_afu_index(struct pci_dev *dev,
398 pci_write_config_byte(dev,
402 rc = read_template_version(dev, fn, &len, &templ_version);
410 dev_dbg(&dev->dev, "AFU descriptor template version %d.%d\n",
422 dev_warn(&dev->dev, "Unknown AFU template version %#x\n",
427 dev_warn(&dev->dev,
433 static int read_afu_name(struct pci_dev *dev, struct ocxl_fn_config *fn,
441 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val);
451 static int read_afu_mmio(struct pci_dev *dev, struct ocxl_fn_config *fn,
460 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val);
466 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val);
471 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val);
479 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val);
485 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val);
490 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val);
498 static int read_afu_control(struct pci_dev *dev, struct ocxl_afu_config *afu)
504 pos = find_dvsec_afu_ctrl(dev, afu->idx);
506 dev_err(&dev->dev, "Can't find AFU control DVSEC for AFU %d\n",
512 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_SUP, &val8);
515 pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP, &val16);
536 static int validate_afu(struct pci_dev *dev, struct ocxl_afu_config *afu)
541 dev_err(&dev->dev, "Empty AFU name\n");
546 dev_err(&dev->dev,
555 dev_err(&dev->dev, "Invalid global MMIO bar number\n");
561 dev_err(&dev->dev, "Invalid per-process MMIO bar number\n");
569 * @dev: the device for the AFU
575 static int read_afu_lpc_memory_info(struct pci_dev *dev,
601 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_ALL_MEM_SZ, &val32);
621 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START, &val32);
627 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START + 4, &val32);
633 rc = read_template_version(dev, fn, &templ_len, &templ_version);
638 rc = read_afu_info(dev, fn,
644 rc = read_afu_info(dev, fn,
663 int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn,
675 pci_write_config_byte(dev,
679 rc = read_afu_name(dev, fn, afu);
683 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_AFU_VERSION, &val32);
692 rc = read_afu_mmio(dev, fn, afu);
696 rc = read_afu_lpc_memory_info(dev, fn, afu);
700 rc = read_afu_control(dev, afu);
704 dev_dbg(&dev->dev, "AFU configuration:\n");
705 dev_dbg(&dev->dev, " name = %s\n", afu->name);
706 dev_dbg(&dev->dev, " version = %d.%d\n", afu->version_major,
708 dev_dbg(&dev->dev, " global mmio bar = %hhu\n", afu->global_mmio_bar);
709 dev_dbg(&dev->dev, " global mmio offset = %#llx\n",
711 dev_dbg(&dev->dev, " global mmio size = %#x\n", afu->global_mmio_size);
712 dev_dbg(&dev->dev, " pp mmio bar = %hhu\n", afu->pp_mmio_bar);
713 dev_dbg(&dev->dev, " pp mmio offset = %#llx\n", afu->pp_mmio_offset);
714 dev_dbg(&dev->dev, " pp mmio stride = %#x\n", afu->pp_mmio_stride);
715 dev_dbg(&dev->dev, " lpc_mem offset = %#llx\n", afu->lpc_mem_offset);
716 dev_dbg(&dev->dev, " lpc_mem size = %#llx\n", afu->lpc_mem_size);
717 dev_dbg(&dev->dev, " special purpose mem offset = %#llx\n",
719 dev_dbg(&dev->dev, " special purpose mem size = %#llx\n",
721 dev_dbg(&dev->dev, " pasid supported (log) = %u\n",
723 dev_dbg(&dev->dev, " actag supported = %u\n",
726 rc = validate_afu(dev, afu);
731 int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled,
741 rc = pnv_ocxl_get_actag(dev, base, enabled, supported);
743 dev_err(&dev->dev, "Can't get actag for device: %d\n", rc);
750 void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base,
756 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val);
759 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
763 int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count)
765 return pnv_ocxl_get_pasid_count(dev, count);
768 void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base,
775 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_EN, val8);
777 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
781 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
786 void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable)
790 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val);
795 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
799 int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec)
811 if (PCI_FUNC(dev->devfn) != 0)
835 rc = pnv_ocxl_get_tl_cap(dev, &recv_cap, recv_rate,
842 pci_write_config_dword(dev,
847 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val);
849 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val);
855 pci_read_config_dword(dev,
861 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val);
863 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val);
866 rc = pnv_ocxl_set_tl_conf(dev, recv_cap, __pa(recv_rate),
888 pci_write_config_byte(dev, tl_dvsec + OCXL_DVSEC_TL_BACKOFF_TIMERS,
898 int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid)
903 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
906 dev_err(&dev->dev,
915 pci_write_config_dword(dev,
920 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
924 dev_err(&dev->dev,
930 pci_read_config_dword(dev,
938 void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first,
945 pci_write_config_dword(dev, func_dvsec + OCXL_DVSEC_FUNC_OFF_ACTAG,