Lines Matching refs:status
388 u32 status;
390 status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG);
391 return !!(SEC_IPC_INPUT_STATUS_RDY & status);
625 .status[0] = PCI_CFG_TXE_FW_STS0,
626 .status[1] = PCI_CFG_TXE_FW_STS1
630 * mei_txe_fw_status - read fw status register from pci config space
633 * @fw_status: fw status register values
650 ret = pci_read_config_dword(pdev, fw_src->status[i],
651 &fw_status->status[i]);
653 fw_src->status[i],
654 fw_status->status[i]);
929 * If HISR.INT2_STS interrupt status bit is set then clear it.