Lines Matching defs:tpc_offset
1808 u32 tpc_offset;
1817 for (tpc_id = 0, tpc_offset = 0;
1819 tpc_id++, tpc_offset += TPC_CFG_OFFSET) {
1821 WREG32(mmTPC0_CFG_TPC_INTR_MASK + tpc_offset, 0x8FFF);
1823 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, tpc_offset,
2242 static void gaudi_init_tpc_qman(struct hl_device *hdev, u32 tpc_offset,
2259 q_off = tpc_offset + qman_id * 4;
2286 tpc_id = tpc_offset /
2295 WREG32(mmTPC0_QM_GLBL_ERR_CFG + tpc_offset, tpc_qm_err_cfg);
2296 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + tpc_offset,
2299 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + tpc_offset,
2302 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + tpc_offset,
2306 WREG32(mmTPC0_QM_ARB_ERR_MSG_EN + tpc_offset,
2310 WREG32(mmTPC0_QM_ARB_SLV_CHOISE_WDT + tpc_offset,
2313 WREG32(mmTPC0_QM_GLBL_CFG1 + tpc_offset, 0);
2314 WREG32(mmTPC0_QM_GLBL_PROT + tpc_offset,
2329 u32 so_base_hi, tpc_offset = 0;
2346 gaudi_init_tpc_qman(hdev, tpc_offset, i,
2351 gaudi_init_tpc_qman(hdev, tpc_offset, 4, 0);
2354 WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset,
2362 tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0;
2409 u32 tpc_offset = 0;
2416 WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset, 0);
2417 tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0;
5635 u32 tpc_offset = tpc_id * TPC_CFG_OFFSET, tpc_interrupts_cause, i;
5647 tpc_interrupts_cause = RREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset) &
5662 WREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset, 0);