Lines Matching refs:afu
89 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
90 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
94 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
103 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
105 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
106 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
110 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
111 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
113 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
268 static void dump_afu_descriptor(struct cxl_afu *afu)
274 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
276 val = AFUD_READ_INFO(afu);
283 val = AFUD_READ(afu, 0x8);
285 val = AFUD_READ(afu, 0x10);
287 val = AFUD_READ(afu, 0x18);
290 val = AFUD_READ_CR(afu);
295 val = AFUD_READ_CR_OFF(afu);
299 val = AFUD_READ_PPPSA(afu);
303 val = AFUD_READ_PPPSA_OFF(afu);
306 val = AFUD_READ_EB(afu);
310 val = AFUD_READ_EB_OFF(afu);
314 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
638 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
643 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
646 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
648 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
650 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
651 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
783 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
789 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
790 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
791 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
792 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
794 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
796 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
799 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
805 iounmap(afu->p2n_mmio);
807 iounmap(afu->native->p1n_mmio);
809 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
813 static void pci_unmap_slice_regs(struct cxl_afu *afu)
815 if (afu->p2n_mmio) {
816 iounmap(afu->p2n_mmio);
817 afu->p2n_mmio = NULL;
819 if (afu->native->p1n_mmio) {
820 iounmap(afu->native->p1n_mmio);
821 afu->native->p1n_mmio = NULL;
823 if (afu->native->afu_desc_mmio) {
824 iounmap(afu->native->afu_desc_mmio);
825 afu->native->afu_desc_mmio = NULL;
831 struct cxl_afu *afu = to_cxl_afu(dev);
835 idr_destroy(&afu->contexts_idr);
836 cxl_release_spa(afu);
838 kfree(afu->native);
839 kfree(afu);
843 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
847 val = AFUD_READ_INFO(afu);
848 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
849 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
850 afu->crs_num = AFUD_NUM_CRS(val);
853 afu->modes_supported |= CXL_MODE_DIRECTED;
855 afu->modes_supported |= CXL_MODE_DEDICATED;
857 afu->modes_supported |= CXL_MODE_TIME_SLICED;
859 val = AFUD_READ_PPPSA(afu);
860 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
861 afu->psa = AFUD_PPPSA_PSA(val);
862 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
863 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
865 val = AFUD_READ_CR(afu);
866 afu->crs_len = AFUD_CR_LEN(val) * 256;
867 afu->crs_offset = AFUD_READ_CR_OFF(afu);
871 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
872 afu->eb_offset = AFUD_READ_EB_OFF(afu);
875 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
876 dev_warn(&afu->dev,
878 afu->eb_offset);
879 dev_info(&afu->dev,
881 /* indicate that no afu buffer exists */
882 afu->eb_len = 0;
888 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
893 if (afu->psa && afu->adapter->ps_size <
894 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
895 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
899 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
900 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
902 for (i = 0; i < afu->crs_num; i++) {
903 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
905 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
910 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
921 dev_err(&afu->dev, "AFU does not support any processes\n");
928 static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
937 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
939 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
940 if (cxl_ops->afu_reset(afu))
942 if (cxl_afu_disable(afu))
944 if (cxl_psl_purge(afu))
947 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
948 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
949 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
951 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
953 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
955 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
957 if (afu->adapter->native->sl_ops->register_serr_irq) {
958 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
961 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
962 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
965 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
967 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
968 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
974 static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
983 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
985 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
986 if (cxl_ops->afu_reset(afu))
988 if (cxl_afu_disable(afu))
990 if (cxl_psl_purge(afu))
993 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
994 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
995 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
996 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
997 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
998 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
999 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1000 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1001 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1002 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1003 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1004 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1006 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1008 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1010 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1012 if (afu->adapter->native->sl_ops->register_serr_irq) {
1013 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1016 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1017 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1020 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1022 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1023 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1032 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1036 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1042 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1044 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1048 count = min((size_t)(afu->eb_len - off), count);
1073 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1077 if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1081 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1087 if ((rc = cxl_ops->afu_reset(afu)))
1091 dump_afu_descriptor(afu);
1093 if ((rc = cxl_read_afu_descriptor(afu)))
1096 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1100 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1104 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1107 if ((rc = cxl_native_register_psl_irq(afu)))
1110 atomic_set(&afu->configured_state, 0);
1115 adapter->native->sl_ops->release_serr_irq(afu);
1117 pci_unmap_slice_regs(afu);
1121 static void pci_deconfigure_afu(struct cxl_afu *afu)
1127 if (atomic_read(&afu->configured_state) != -1) {
1128 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1131 cxl_native_release_psl_irq(afu);
1132 if (afu->adapter->native->sl_ops->release_serr_irq)
1133 afu->adapter->native->sl_ops->release_serr_irq(afu);
1134 pci_unmap_slice_regs(afu);
1139 struct cxl_afu *afu;
1142 afu = cxl_alloc_afu(adapter, slice);
1143 if (!afu)
1146 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1147 if (!afu->native)
1150 mutex_init(&afu->native->spa_mutex);
1152 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1156 rc = pci_configure_afu(afu, adapter, dev);
1161 cxl_debugfs_afu_add(afu);
1164 * After we call this function we must not free the afu directly, even
1167 if ((rc = cxl_register_afu(afu)))
1170 if ((rc = cxl_sysfs_afu_add(afu)))
1173 adapter->afu[afu->slice] = afu;
1175 if ((rc = cxl_pci_vphb_add(afu)))
1176 dev_info(&afu->dev, "Can't register vPHB\n");
1181 device_del(&afu->dev);
1183 pci_deconfigure_afu(afu);
1184 cxl_debugfs_afu_remove(afu);
1185 put_device(&afu->dev);
1189 kfree(afu->native);
1191 kfree(afu);
1196 static void cxl_pci_remove_afu(struct cxl_afu *afu)
1200 if (!afu)
1203 cxl_pci_vphb_remove(afu);
1204 cxl_sysfs_afu_remove(afu);
1205 cxl_debugfs_afu_remove(afu);
1207 spin_lock(&afu->adapter->afu_list_lock);
1208 afu->adapter->afu[afu->slice] = NULL;
1209 spin_unlock(&afu->adapter->afu_list_lock);
1211 cxl_context_detach_all(afu);
1212 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1214 pci_deconfigure_afu(afu);
1215 device_unregister(&afu->dev);
1570 if (adapter->afu[slice])
1571 cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
1774 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1785 struct cxl_afu *afu;
1793 afu = adapter->afu[i];
1794 cxl_pci_remove_afu(afu);
1799 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
1809 if (afu == NULL || afu->phb == NULL)
1812 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1835 struct cxl_afu *afu;
1850 afu = adapter->afu[i];
1855 cxl_vphb_error_detected(afu, state);
1940 /* Make sure no one else changes the afu list */
1944 afu = adapter->afu[i];
1946 if (afu == NULL)
1949 afu_result = cxl_vphb_error_detected(afu, state);
1950 cxl_context_detach_all(afu);
1951 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1952 pci_deconfigure_afu(afu);
1977 struct cxl_afu *afu;
1996 afu = adapter->afu[i];
1998 if (afu == NULL)
2001 if (pci_configure_afu(afu, adapter, pdev))
2004 if (cxl_afu_select_best_mode(afu))
2007 if (afu->phb == NULL)
2010 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2025 if (cxl_ops->afu_check_and_enable(afu))
2066 struct cxl_afu *afu;
2076 afu = adapter->afu[i];
2078 if (afu == NULL || afu->phb == NULL)
2081 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {