Lines Matching refs:ctx
408 static void slb_invalid(struct cxl_context *ctx)
410 struct cxl *adapter = ctx->afu->adapter;
413 WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex));
416 ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) |
417 be32_to_cpu(ctx->elem->lpid));
430 static int do_process_element_cmd(struct cxl_context *ctx,
437 trace_cxl_llcmd(ctx, cmd);
439 WARN_ON(!ctx->afu->enabled);
441 ctx->elem->software_state = cpu_to_be32(pe_state);
443 *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
445 cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
448 dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
452 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
453 dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
457 state = be64_to_cpup(ctx->afu->native->sw_command_status);
464 (cmd | (cmd >> 16) | ctx->pe))
477 trace_cxl_llcmd_done(ctx, cmd, rc);
481 static int add_process_element(struct cxl_context *ctx)
485 mutex_lock(&ctx->afu->native->spa_mutex);
486 pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
487 if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V)))
488 ctx->pe_inserted = true;
489 pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
490 mutex_unlock(&ctx->afu->native->spa_mutex);
494 static int terminate_process_element(struct cxl_context *ctx)
499 if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V)))
502 mutex_lock(&ctx->afu->native->spa_mutex);
503 pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
508 if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
509 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
511 ctx->elem->software_state = 0; /* Remove Valid bit */
512 pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
513 mutex_unlock(&ctx->afu->native->spa_mutex);
517 static int remove_process_element(struct cxl_context *ctx)
521 mutex_lock(&ctx->afu->native->spa_mutex);
522 pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
527 if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
528 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0);
531 ctx->pe_inserted = false;
533 slb_invalid(ctx);
534 pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
535 mutex_unlock(&ctx->afu->native->spa_mutex);
540 void cxl_assign_psn_space(struct cxl_context *ctx)
542 if (!ctx->afu->pp_size || ctx->master) {
543 ctx->psn_phys = ctx->afu->psn_phys;
544 ctx->psn_size = ctx->afu->adapter->ps_size;
546 ctx->psn_phys = ctx->afu->psn_phys +
547 (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe);
548 ctx->psn_size = ctx->afu->pp_size;
627 static u64 calculate_sr(struct cxl_context *ctx)
629 return cxl_calculate_sr(ctx->master, ctx->kernel, false,
633 static void update_ivtes_directed(struct cxl_context *ctx)
635 bool need_update = (ctx->status == STARTED);
639 WARN_ON(terminate_process_element(ctx));
640 WARN_ON(remove_process_element(ctx));
644 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
645 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
659 WARN_ON(add_process_element(ctx));
662 static int process_element_entry_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
667 cxl_assign_psn_space(ctx);
669 ctx->elem->ctxtime = 0; /* disable */
670 ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
671 ctx->elem->haurp = 0; /* disable */
673 if (ctx->kernel)
676 if (ctx->mm == NULL) {
678 __func__, ctx->pe, pid_nr(ctx->pid));
681 pid = ctx->mm->context.id;
685 if (!(ctx->tidr) && (ctx->assign_tidr)) {
689 ctx->tidr = current->thread.tidr;
690 pr_devel("%s: current tidr: %d\n", __func__, ctx->tidr);
693 ctx->elem->common.tid = cpu_to_be32(ctx->tidr);
694 ctx->elem->common.pid = cpu_to_be32(pid);
696 ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
698 ctx->elem->common.csrp = 0; /* disable */
700 cxl_prefault(ctx, wed);
706 if (ctx->irqs.range[0] == 0) {
707 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
708 ctx->irqs.range[0] = 1;
711 ctx->elem->common.amr = cpu_to_be64(amr);
712 ctx->elem->common.wed = cpu_to_be64(wed);
717 int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
722 result = process_element_entry_psl9(ctx, wed, amr);
726 update_ivtes_directed(ctx);
729 result = cxl_ops->afu_check_and_enable(ctx->afu);
733 return add_process_element(ctx);
736 int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
741 cxl_assign_psn_space(ctx);
743 ctx->elem->ctxtime = 0; /* disable */
744 ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
745 ctx->elem->haurp = 0; /* disable */
746 ctx->elem->u.sdr = cpu_to_be64(mfspr(SPRN_SDR1));
749 if (ctx->kernel)
751 ctx->elem->common.tid = 0;
752 ctx->elem->common.pid = cpu_to_be32(pid);
754 ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
756 ctx->elem->common.csrp = 0; /* disable */
757 ctx->elem->common.u.psl8.aurp0 = 0; /* disable */
758 ctx->elem->common.u.psl8.aurp1 = 0; /* disable */
760 cxl_prefault(ctx, wed);
762 ctx->elem->common.u.psl8.sstp0 = cpu_to_be64(ctx->sstp0);
763 ctx->elem->common.u.psl8.sstp1 = cpu_to_be64(ctx->sstp1);
769 if (ctx->irqs.range[0] == 0) {
770 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
771 ctx->irqs.range[0] = 1;
774 update_ivtes_directed(ctx);
776 ctx->elem->common.amr = cpu_to_be64(amr);
777 ctx->elem->common.wed = cpu_to_be64(wed);
780 if ((result = cxl_ops->afu_check_and_enable(ctx->afu)))
783 return add_process_element(ctx);
878 void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx)
883 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
884 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
888 void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx)
890 struct cxl_afu *afu = ctx->afu;
893 (((u64)ctx->irqs.offset[0] & 0xffff) << 48) |
894 (((u64)ctx->irqs.offset[1] & 0xffff) << 32) |
895 (((u64)ctx->irqs.offset[2] & 0xffff) << 16) |
896 ((u64)ctx->irqs.offset[3] & 0xffff));
898 (((u64)ctx->irqs.range[0] & 0xffff) << 48) |
899 (((u64)ctx->irqs.range[1] & 0xffff) << 32) |
900 (((u64)ctx->irqs.range[2] & 0xffff) << 16) |
901 ((u64)ctx->irqs.range[3] & 0xffff));
904 int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
906 struct cxl_afu *afu = ctx->afu;
910 result = process_element_entry_psl9(ctx, wed, amr);
914 if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
915 afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
917 ctx->elem->software_state = cpu_to_be32(CXL_PE_SOFTWARE_STATE_V);
932 int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
934 struct cxl_afu *afu = ctx->afu;
939 if (ctx->kernel)
943 cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
945 if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
948 cxl_prefault(ctx, wed);
950 if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
951 afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
956 cxl_assign_psn_space(ctx);
1008 static int native_attach_process(struct cxl_context *ctx, bool kernel,
1011 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
1016 ctx->kernel = kernel;
1017 if ((ctx->afu->current_mode == CXL_MODE_DIRECTED) &&
1018 (ctx->afu->adapter->native->sl_ops->attach_afu_directed))
1019 return ctx->afu->adapter->native->sl_ops->attach_afu_directed(ctx, wed, amr);
1021 if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
1022 (ctx->afu->adapter->native->sl_ops->attach_dedicated_process))
1023 return ctx->afu->adapter->native->sl_ops->attach_dedicated_process(ctx, wed, amr);
1028 static inline int detach_process_native_dedicated(struct cxl_context *ctx)
1046 cxl_ops->afu_reset(ctx->afu);
1047 cxl_afu_disable(ctx->afu);
1048 cxl_psl_purge(ctx->afu);
1052 static void native_update_ivtes(struct cxl_context *ctx)
1054 if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
1055 return update_ivtes_directed(ctx);
1056 if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
1057 (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes))
1058 return ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
1062 static inline int detach_process_native_afu_directed(struct cxl_context *ctx)
1064 if (!ctx->pe_inserted)
1066 if (terminate_process_element(ctx))
1068 if (remove_process_element(ctx))
1074 static int native_detach_process(struct cxl_context *ctx)
1076 trace_cxl_detach(ctx);
1078 if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
1079 return detach_process_native_dedicated(ctx);
1081 return detach_process_native_afu_directed(ctx);
1103 void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx)
1107 fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR1);
1109 dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
1110 if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
1111 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
1112 cxl_afu_decode_psl_serr(ctx->afu, serr);
1116 void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx)
1120 fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1);
1121 fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2);
1122 fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An);
1123 afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
1125 dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
1126 dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
1127 if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
1128 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
1129 cxl_afu_decode_psl_serr(ctx->afu, serr);
1131 dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
1132 dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
1135 static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx,
1139 dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat);
1141 if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers)
1142 ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx);
1144 if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) {
1145 dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
1146 ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter);
1149 return cxl_ops->ack_irq(ctx, 0, errstat);
1176 struct cxl_context *ctx;
1198 ctx = idr_find(&afu->contexts_idr, ph);
1199 if (ctx) {
1201 ret = afu->adapter->native->sl_ops->handle_interrupt(irq, ctx, &irq_info);
1216 static void native_irq_wait(struct cxl_context *ctx)
1227 ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff;
1228 if (ph != ctx->pe)
1230 dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An);
1244 dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i"
1451 static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
1453 trace_cxl_psl_irq_ack(ctx, tfc);
1455 cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
1457 recover_psl_err(ctx->afu, psl_reset_mask);