Lines Matching refs:dsisr
25 static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar)
27 ctx->dsisr = dsisr;
35 u64 dsisr, dar;
37 dsisr = irq_info->dsisr;
40 trace_cxl_psl9_irq(ctx, irq, dsisr, dar);
42 pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);
44 if (dsisr & CXL_PSL9_DSISR_An_TF) {
46 return schedule_cxl_fault(ctx, dsisr, dar);
49 if (dsisr & CXL_PSL9_DSISR_An_PE)
50 return cxl_ops->handle_psl_slice_error(ctx, dsisr,
52 if (dsisr & CXL_PSL9_DSISR_An_AE) {
77 if (dsisr & CXL_PSL9_DSISR_An_OC)
86 u64 dsisr, dar;
88 dsisr = irq_info->dsisr;
91 trace_cxl_psl_irq(ctx, irq, dsisr, dar);
93 pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);
95 if (dsisr & CXL_PSL_DSISR_An_DS) {
107 return schedule_cxl_fault(ctx, dsisr, dar);
110 if (dsisr & CXL_PSL_DSISR_An_M)
112 if (dsisr & CXL_PSL_DSISR_An_P)
114 if (dsisr & CXL_PSL_DSISR_An_A)
116 if (dsisr & CXL_PSL_DSISR_An_S)
118 if (dsisr & CXL_PSL_DSISR_An_K)
121 if (dsisr & CXL_PSL_DSISR_An_DM) {
128 return schedule_cxl_fault(ctx, dsisr, dar);
130 if (dsisr & CXL_PSL_DSISR_An_ST)
132 if (dsisr & CXL_PSL_DSISR_An_UR)
134 if (dsisr & CXL_PSL_DSISR_An_PE)
135 return cxl_ops->handle_psl_slice_error(ctx, dsisr,
137 if (dsisr & CXL_PSL_DSISR_An_AE) {
163 if (dsisr & CXL_PSL_DSISR_An_OC)