Lines Matching refs:pcr
60 static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
62 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
66 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
68 rtsx_pci_write_register(pcr, MSGTXDATA0,
70 rtsx_pci_write_register(pcr, MSGTXDATA1,
72 rtsx_pci_write_register(pcr, MSGTXDATA2,
74 rtsx_pci_write_register(pcr, MSGTXDATA3,
76 rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK |
82 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
84 return rtsx_comm_set_ltr_latency(pcr, latency);
87 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
89 if (pcr->aspm_enabled == enable)
92 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
94 enable ? pcr->aspm_en : 0);
96 pcr->aspm_enabled = enable;
99 static void rtsx_disable_aspm(struct rtsx_pcr *pcr)
101 if (pcr->ops->set_aspm)
102 pcr->ops->set_aspm(pcr, false);
104 rtsx_comm_set_aspm(pcr, false);
107 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val)
109 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val);
114 static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active)
116 if (pcr->ops->set_l1off_cfg_sub_d0)
117 pcr->ops->set_l1off_cfg_sub_d0(pcr, active);
120 static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr)
122 struct rtsx_cr_option *option = &pcr->option;
124 rtsx_disable_aspm(pcr);
130 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
132 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
133 rtsx_set_l1off_sub_cfg_d0(pcr, 1);
136 static void rtsx_pm_full_on(struct rtsx_pcr *pcr)
138 rtsx_comm_pm_full_on(pcr);
141 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
144 if (pcr->remove_pci)
147 if (pcr->state != PDEV_STAT_RUN) {
148 pcr->state = PDEV_STAT_RUN;
149 if (pcr->ops->enable_auto_blink)
150 pcr->ops->enable_auto_blink(pcr);
151 rtsx_pm_full_on(pcr);
154 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
158 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
167 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
170 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
182 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
188 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
191 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
206 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
211 rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val);
212 rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8));
213 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
214 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81);
217 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
233 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
235 if (pcr->ops->write_phy)
236 return pcr->ops->write_phy(pcr, addr, val);
238 return __rtsx_pci_write_phy_register(pcr, addr, val);
242 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
248 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
249 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80);
252 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
265 rtsx_pci_read_register(pcr, PHYDATA0, &val1);
266 rtsx_pci_read_register(pcr, PHYDATA1, &val2);
275 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
277 if (pcr->ops->read_phy)
278 return pcr->ops->read_phy(pcr, addr, val);
280 return __rtsx_pci_read_phy_register(pcr, addr, val);
284 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
286 if (pcr->ops->stop_cmd)
287 return pcr->ops->stop_cmd(pcr);
289 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
290 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
292 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
293 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
297 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
302 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
309 spin_lock_irqsave(&pcr->lock, flags);
310 ptr += pcr->ci;
311 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
314 pcr->ci++;
316 spin_unlock_irqrestore(&pcr->lock, flags);
320 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
324 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
326 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
329 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
333 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
341 spin_lock_irqsave(&pcr->lock, flags);
344 pcr->done = &trans_done;
345 pcr->trans_result = TRANS_NOT_READY;
348 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
350 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
353 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
355 spin_unlock_irqrestore(&pcr->lock, flags);
361 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
366 spin_lock_irqsave(&pcr->lock, flags);
367 if (pcr->trans_result == TRANS_RESULT_FAIL)
369 else if (pcr->trans_result == TRANS_RESULT_OK)
371 else if (pcr->trans_result == TRANS_NO_DEVICE)
373 spin_unlock_irqrestore(&pcr->lock, flags);
376 spin_lock_irqsave(&pcr->lock, flags);
377 pcr->done = NULL;
378 spin_unlock_irqrestore(&pcr->lock, flags);
381 rtsx_pci_stop_cmd(pcr);
383 if (pcr->finish_me)
384 complete(pcr->finish_me);
390 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
393 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
397 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
402 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) {
412 pcr->sgi++;
415 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
420 pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
421 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
424 pcr_dbg(pcr, "DMA mapping count: %d\n", count);
426 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
428 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
434 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
439 if (pcr->remove_pci)
445 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
449 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
454 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
458 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
471 if (pcr->remove_pci)
478 pcr->sgi = 0;
482 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
485 spin_lock_irqsave(&pcr->lock, flags);
487 pcr->done = &trans_done;
488 pcr->trans_result = TRANS_NOT_READY;
490 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
491 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
493 spin_unlock_irqrestore(&pcr->lock, flags);
498 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
503 spin_lock_irqsave(&pcr->lock, flags);
504 if (pcr->trans_result == TRANS_RESULT_FAIL) {
506 if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION)
507 pcr->dma_error_count++;
510 else if (pcr->trans_result == TRANS_NO_DEVICE)
512 spin_unlock_irqrestore(&pcr->lock, flags);
515 spin_lock_irqsave(&pcr->lock, flags);
516 pcr->done = NULL;
517 spin_unlock_irqrestore(&pcr->lock, flags);
520 rtsx_pci_stop_cmd(pcr);
522 if (pcr->finish_me)
523 complete(pcr->finish_me);
529 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
542 rtsx_pci_init_cmd(pcr);
545 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
547 err = rtsx_pci_send_cmd(pcr, 250);
551 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
556 rtsx_pci_init_cmd(pcr);
559 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
561 err = rtsx_pci_send_cmd(pcr, 250);
566 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
572 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
585 rtsx_pci_init_cmd(pcr);
588 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
593 err = rtsx_pci_send_cmd(pcr, 250);
599 rtsx_pci_init_cmd(pcr);
602 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
607 err = rtsx_pci_send_cmd(pcr, 250);
616 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
618 rtsx_pci_init_cmd(pcr);
621 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
626 return rtsx_pci_send_cmd(pcr, 100);
629 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
634 tbl = pcr->sd_pull_ctl_enable_tbl;
636 tbl = pcr->ms_pull_ctl_enable_tbl;
640 return rtsx_pci_set_pull_ctl(pcr, tbl);
644 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
649 tbl = pcr->sd_pull_ctl_disable_tbl;
651 tbl = pcr->ms_pull_ctl_disable_tbl;
655 return rtsx_pci_set_pull_ctl(pcr, tbl);
659 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
661 struct rtsx_hw_param *hw_param = &pcr->hw_param;
663 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN
666 if (pcr->num_slots > 1)
667 pcr->bier |= MS_INT_EN;
670 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
672 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
692 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
705 if (PCI_PID(pcr) == PID_5261)
706 return rts5261_pci_switch_clock(pcr, card_clock,
708 if (PCI_PID(pcr) == PID_5228)
709 return rts5228_pci_switch_clock(pcr, card_clock,
719 err = rtsx_pci_write_register(pcr, SD_CFG1,
726 pcr->dma_error_count &&
727 PCI_PID(pcr) == RTS5227_DEVICE_ID)
729 (pcr->dma_error_count * 20000000);
732 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
737 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
738 clk, pcr->cur_clock);
740 if (clk == pcr->cur_clock)
743 if (pcr->ops->conv_clk_and_div_n)
744 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
757 if (pcr->ops->conv_clk_and_div_n) {
758 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
760 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
767 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
774 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
776 rtsx_pci_init_cmd(pcr);
777 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
779 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
781 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
782 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
784 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
785 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
787 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
789 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
793 err = rtsx_pci_send_cmd(pcr, 2000);
799 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
803 pcr->cur_clock = clk;
808 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
810 if (pcr->ops->card_power_on)
811 return pcr->ops->card_power_on(pcr, card);
817 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
819 if (pcr->ops->card_power_off)
820 return pcr->ops->card_power_off(pcr, card);
826 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
833 if (!(pcr->flags & PCR_MS_PMOS)) {
837 if (pcr->card_exist & (~cd_mask[card]))
845 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
847 if (pcr->ops->switch_output_voltage)
848 return pcr->ops->switch_output_voltage(pcr, voltage);
854 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
858 val = rtsx_pci_readl(pcr, RTSX_BIPR);
859 if (pcr->ops->cd_deglitch)
860 val = pcr->ops->cd_deglitch(pcr);
866 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
870 pcr->finish_me = &finish;
873 if (pcr->done)
874 complete(pcr->done);
876 if (!pcr->remove_pci)
877 rtsx_pci_stop_cmd(pcr);
881 pcr->finish_me = NULL;
888 struct rtsx_pcr *pcr;
894 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
896 pcr_dbg(pcr, "--> %s\n", __func__);
898 mutex_lock(&pcr->pcr_mutex);
899 spin_lock_irqsave(&pcr->lock, flags);
901 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
902 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
905 card_inserted = pcr->card_inserted & irq_status;
906 card_removed = pcr->card_removed;
907 pcr->card_inserted = 0;
908 pcr->card_removed = 0;
910 spin_unlock_irqrestore(&pcr->lock, flags);
913 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
916 if (pcr->ops->cd_deglitch)
917 card_inserted = pcr->ops->cd_deglitch(pcr);
921 pcr->card_exist |= card_inserted;
922 pcr->card_exist &= ~card_removed;
925 mutex_unlock(&pcr->pcr_mutex);
927 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
928 pcr->slots[RTSX_SD_CARD].card_event(
929 pcr->slots[RTSX_SD_CARD].p_dev);
930 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
931 pcr->slots[RTSX_MS_CARD].card_event(
932 pcr->slots[RTSX_MS_CARD].p_dev);
935 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
937 if (pcr->ops->process_ocp) {
938 pcr->ops->process_ocp(pcr);
940 if (!pcr->option.ocp_en)
942 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
943 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
944 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
945 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
946 rtsx_pci_clear_ocpstat(pcr);
947 pcr->ocp_stat = 0;
952 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
954 if (pcr->option.ocp_en)
955 rtsx_pci_process_ocp(pcr);
962 struct rtsx_pcr *pcr = dev_id;
965 if (!pcr)
968 spin_lock(&pcr->lock);
970 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
972 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
973 if ((int_reg & pcr->bier) == 0) {
974 spin_unlock(&pcr->lock);
978 spin_unlock(&pcr->lock);
982 int_reg &= (pcr->bier | 0x7FFFFF);
985 rtsx_pci_process_ocp_interrupt(pcr);
989 pcr->card_inserted |= SD_EXIST;
991 pcr->card_removed |= SD_EXIST;
992 pcr->card_inserted &= ~SD_EXIST;
994 pcr->dma_error_count = 0;
999 pcr->card_inserted |= MS_EXIST;
1001 pcr->card_removed |= MS_EXIST;
1002 pcr->card_inserted &= ~MS_EXIST;
1008 pcr->trans_result = TRANS_RESULT_FAIL;
1009 if (pcr->done)
1010 complete(pcr->done);
1012 pcr->trans_result = TRANS_RESULT_OK;
1013 if (pcr->done)
1014 complete(pcr->done);
1018 if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT))
1019 schedule_delayed_work(&pcr->carddet_work,
1022 spin_unlock(&pcr->lock);
1026 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
1028 pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n",
1029 __func__, pcr->msi_en, pcr->pci->irq);
1031 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
1032 pcr->msi_en ? 0 : IRQF_SHARED,
1033 DRV_NAME_RTSX_PCI, pcr)) {
1034 dev_err(&(pcr->pci->dev),
1036 pcr->pci->irq);
1040 pcr->irq = pcr->pci->irq;
1041 pci_intx(pcr->pci, !pcr->msi_en);
1046 static void rtsx_enable_aspm(struct rtsx_pcr *pcr)
1048 if (pcr->ops->set_aspm)
1049 pcr->ops->set_aspm(pcr, true);
1051 rtsx_comm_set_aspm(pcr, true);
1054 static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr)
1056 struct rtsx_cr_option *option = &pcr->option;
1061 if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN))
1064 rtsx_set_ltr_latency(pcr, latency);
1067 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
1068 rtsx_set_l1off_sub_cfg_d0(pcr, 0);
1070 rtsx_enable_aspm(pcr);
1073 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr)
1075 rtsx_comm_pm_power_saving(pcr);
1081 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
1083 pcr_dbg(pcr, "--> %s\n", __func__);
1085 mutex_lock(&pcr->pcr_mutex);
1087 pcr->state = PDEV_STAT_IDLE;
1089 if (pcr->ops->disable_auto_blink)
1090 pcr->ops->disable_auto_blink(pcr);
1091 if (pcr->ops->turn_off_led)
1092 pcr->ops->turn_off_led(pcr);
1094 rtsx_pm_power_saving(pcr);
1096 mutex_unlock(&pcr->pcr_mutex);
1099 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
1102 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
1103 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
1104 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
1107 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
1110 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
1113 static void __maybe_unused rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
1115 if (pcr->ops->turn_off_led)
1116 pcr->ops->turn_off_led(pcr);
1118 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1119 pcr->bier = 0;
1121 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1122 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
1124 if (pcr->ops->force_power_down)
1125 pcr->ops->force_power_down(pcr, pm_state);
1127 rtsx_base_force_power_down(pcr, pm_state);
1130 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
1134 if (pcr->ops->enable_ocp) {
1135 pcr->ops->enable_ocp(pcr);
1137 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1138 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
1143 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
1147 if (pcr->ops->disable_ocp) {
1148 pcr->ops->disable_ocp(pcr);
1150 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1151 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
1156 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
1158 if (pcr->ops->init_ocp) {
1159 pcr->ops->init_ocp(pcr);
1161 struct rtsx_cr_option *option = &(pcr->option);
1166 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1167 rtsx_pci_write_register(pcr, REG_OCPPARA1,
1169 rtsx_pci_write_register(pcr, REG_OCPPARA2,
1171 rtsx_pci_write_register(pcr, REG_OCPGLITCH,
1172 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);
1173 rtsx_pci_enable_ocp(pcr);
1178 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
1180 if (pcr->ops->get_ocpstat)
1181 return pcr->ops->get_ocpstat(pcr, val);
1183 return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
1186 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr)
1188 if (pcr->ops->clear_ocpstat) {
1189 pcr->ops->clear_ocpstat(pcr);
1194 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1196 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1200 void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr)
1204 if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1205 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1207 rtsx_pci_write_phy_register(pcr, 0x01, val);
1209 rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32);
1210 rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05);
1211 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83);
1212 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE);
1216 void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr)
1220 if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1221 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1223 rtsx_pci_write_phy_register(pcr, 0x01, val);
1225 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03);
1226 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00);
1230 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
1232 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1234 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1235 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1239 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1244 int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr)
1246 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1249 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
1251 rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0);
1252 rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
1257 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
1259 struct pci_dev *pdev = pcr->pci;
1262 if (PCI_PID(pcr) == PID_5228)
1263 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK,
1266 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1268 rtsx_pci_enable_bus_int(pcr);
1271 if (PCI_PID(pcr) == PID_5261) {
1273 err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1275 err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
1278 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1286 rtsx_pci_disable_aspm(pcr);
1287 if (pcr->ops->optimize_phy) {
1288 err = pcr->ops->optimize_phy(pcr);
1293 rtsx_pci_init_cmd(pcr);
1296 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1298 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1300 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
1302 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1304 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1305 0xFF, pcr->card_drive_sel);
1307 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1309 if (PCI_PID(pcr) == PID_5261)
1310 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1312 else if (PCI_PID(pcr) == PID_5228)
1313 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1316 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1319 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1321 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1326 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1331 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1337 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1339 err = rtsx_pci_send_cmd(pcr, 100);
1343 switch (PCI_PID(pcr)) {
1350 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
1357 rtsx_pci_init_ocp(pcr);
1365 if (pcr->ops->extra_init_hw) {
1366 err = pcr->ops->extra_init_hw(pcr);
1372 * So we need to initialize pcr->card_exist here.
1374 if (pcr->ops->cd_deglitch)
1375 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1377 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1382 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1386 spin_lock_init(&pcr->lock);
1387 mutex_init(&pcr->pcr_mutex);
1389 switch (PCI_PID(pcr)) {
1392 rts5209_init_params(pcr);
1396 rts5229_init_params(pcr);
1400 rtl8411_init_params(pcr);
1404 rts5227_init_params(pcr);
1408 rts522a_init_params(pcr);
1412 rts5249_init_params(pcr);
1416 rts524a_init_params(pcr);
1420 rts525a_init_params(pcr);
1424 rtl8411b_init_params(pcr);
1428 rtl8402_init_params(pcr);
1432 rts5260_init_params(pcr);
1436 rts5261_init_params(pcr);
1440 rts5228_init_params(pcr);
1444 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1445 PCI_PID(pcr), pcr->ic_version);
1447 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1449 if (!pcr->slots)
1452 if (pcr->ops->fetch_vendor_settings)
1453 pcr->ops->fetch_vendor_settings(pcr);
1455 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1456 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1457 pcr->sd30_drive_sel_1v8);
1458 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1459 pcr->sd30_drive_sel_3v3);
1460 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
1461 pcr->card_drive_sel);
1462 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
1464 pcr->state = PDEV_STAT_IDLE;
1465 err = rtsx_pci_init_hw(pcr);
1467 kfree(pcr->slots);
1477 struct rtsx_pcr *pcr;
1499 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1500 if (!pcr) {
1510 handle->pcr = pcr;
1514 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1516 pcr->id = ret;
1522 pcr->pci = pcidev;
1525 if (CHK_PCI_PID(pcr, 0x525A))
1529 pcr->remap_addr = ioremap(base, len);
1530 if (!pcr->remap_addr) {
1535 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1536 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1538 if (pcr->rtsx_resv_buf == NULL) {
1542 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1543 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1544 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1545 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1547 pcr->card_inserted = 0;
1548 pcr->card_removed = 0;
1549 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1550 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1552 pcr->msi_en = msi_en;
1553 if (pcr->msi_en) {
1556 pcr->msi_en = false;
1559 ret = rtsx_pci_acquire_irq(pcr);
1564 synchronize_irq(pcr->irq);
1566 ret = rtsx_pci_init_chip(pcr);
1574 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1579 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1584 kfree(pcr->slots);
1586 free_irq(pcr->irq, (void *)pcr);
1588 if (pcr->msi_en)
1589 pci_disable_msi(pcr->pci);
1590 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1591 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1593 iounmap(pcr->remap_addr);
1596 idr_remove(&rtsx_pci_idr, pcr->id);
1601 kfree(pcr);
1613 struct rtsx_pcr *pcr = handle->pcr;
1615 pcr->remove_pci = true;
1617 /* Disable interrupts at the pcr level */
1618 spin_lock_irq(&pcr->lock);
1619 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1620 pcr->bier = 0;
1621 spin_unlock_irq(&pcr->lock);
1623 cancel_delayed_work_sync(&pcr->carddet_work);
1624 cancel_delayed_work_sync(&pcr->idle_work);
1628 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1629 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1630 free_irq(pcr->irq, (void *)pcr);
1631 if (pcr->msi_en)
1632 pci_disable_msi(pcr->pci);
1633 iounmap(pcr->remap_addr);
1639 idr_remove(&rtsx_pci_idr, pcr->id);
1642 kfree(pcr->slots);
1643 kfree(pcr);
1655 struct rtsx_pcr *pcr;
1660 pcr = handle->pcr;
1662 cancel_delayed_work(&pcr->carddet_work);
1663 cancel_delayed_work(&pcr->idle_work);
1665 mutex_lock(&pcr->pcr_mutex);
1667 rtsx_pci_power_off(pcr, HOST_ENTER_S3);
1671 mutex_unlock(&pcr->pcr_mutex);
1679 struct rtsx_pcr *pcr;
1685 pcr = handle->pcr;
1687 mutex_lock(&pcr->pcr_mutex);
1689 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1693 ret = rtsx_pci_init_hw(pcr);
1697 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1700 mutex_unlock(&pcr->pcr_mutex);
1709 struct rtsx_pcr *pcr;
1714 pcr = handle->pcr;
1715 rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1718 free_irq(pcr->irq, (void *)pcr);
1719 if (pcr->msi_en)
1720 pci_disable_msi(pcr->pci);