Lines Matching refs:pcr
18 static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr)
22 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
26 static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
44 drive_sel = pcr->sd30_drive_sel_3v3;
47 drive_sel = pcr->sd30_drive_sel_1v8;
50 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
53 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
56 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
60 static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr)
62 struct pci_dev *pdev = pcr->pci;
67 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
70 pcr_dbg(pcr, "skip fetch vendor setting\n");
74 pcr->card_drive_sel &= 0x3F;
75 pcr->card_drive_sel |= rts5261_reg_to_card_drive_sel(reg);
78 pcr->flags |= PCR_REVERSE_SOCKET;
82 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
84 pcr->aspm_en = rts5261_reg_to_aspm(reg);
85 pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg);
86 pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg);
89 static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
92 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
93 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
94 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
98 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
101 rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
105 static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr)
107 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
111 static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr)
113 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
117 static int rts5261_turn_on_led(struct rtsx_pcr *pcr)
119 return rtsx_pci_write_register(pcr, GPIO_CTL,
123 static int rts5261_turn_off_led(struct rtsx_pcr *pcr)
125 return rtsx_pci_write_register(pcr, GPIO_CTL,
155 static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
157 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
159 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
160 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
162 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
167 static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card)
169 struct rtsx_cr_option *option = &pcr->option;
172 rtsx_pci_enable_ocp(pcr);
175 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1,
177 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
180 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
185 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
188 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
191 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
193 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
194 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
198 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
199 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
203 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
204 pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
205 rts5261_sd_set_sample_push_timing_sd30(pcr);
210 static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
215 rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL,
220 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
222 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
226 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
228 rtsx_pci_write_register(pcr, SD_PAD_CTL,
232 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
234 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
238 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
240 rtsx_pci_write_register(pcr, SD_PAD_CTL,
248 rts5261_fill_driving(pcr, voltage);
253 static void rts5261_stop_cmd(struct rtsx_pcr *pcr)
255 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
256 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
257 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
260 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
263 static void rts5261_card_before_power_off(struct rtsx_pcr *pcr)
265 rts5261_stop_cmd(pcr);
266 rts5261_switch_output_voltage(pcr, OUTPUT_3V3);
270 static void rts5261_enable_ocp(struct rtsx_pcr *pcr)
275 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
279 static void rts5261_disable_ocp(struct rtsx_pcr *pcr)
284 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
285 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
290 static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card)
294 rts5261_card_before_power_off(pcr);
295 err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
298 if (pcr->option.ocp_en)
299 rtsx_pci_disable_ocp(pcr);
304 static void rts5261_init_ocp(struct rtsx_pcr *pcr)
306 struct rtsx_cr_option *option = &pcr->option;
311 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
315 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
318 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
323 val = pcr->hw_param.ocp_glitch;
324 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
326 rts5261_enable_ocp(pcr);
328 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
333 static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr)
341 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
344 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
348 static void rts5261_process_ocp(struct rtsx_pcr *pcr)
350 if (!pcr->option.ocp_en)
353 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
355 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
356 rts5261_card_power_off(pcr, RTSX_SD_CARD);
357 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
358 rts5261_clear_ocpstat(pcr);
359 pcr->ocp_stat = 0;
364 static int rts5261_init_from_hw(struct rtsx_pcr *pcr)
366 struct pci_dev *pdev = pcr->pci;
371 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
375 rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR,
377 rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL,
383 rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp);
387 rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
389 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
394 pcr_dbg(pcr, "read 0x814 DW fail\n");
395 pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval);
398 pcr_dbg(pcr, "0x816: %d\n", valid);
400 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
402 pcr_dbg(pcr, "Disable efuse por!\n");
408 pcr_dbg(pcr, "write config fail\n");
413 static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
415 struct pci_dev *pdev = pcr->pci;
418 struct rtsx_cr_option *option = &pcr->option;
427 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
429 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
432 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
434 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
437 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
439 rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
442 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
444 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
446 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
454 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
460 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
467 static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
469 struct rtsx_cr_option *option = &pcr->option;
471 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
474 rts5261_init_from_cfg(pcr);
475 rts5261_init_from_hw(pcr);
478 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
480 rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
482 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
484 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
488 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
490 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
493 rtsx_pci_write_register(pcr, PCLK_CTL,
496 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
497 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
500 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
503 rts5261_fill_driving(pcr, OUTPUT_3V3);
510 rtsx_pci_write_register(pcr, PETXCFG,
513 rtsx_pci_write_register(pcr, PETXCFG,
516 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
517 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
521 rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
527 static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
529 if (pcr->aspm_enabled == enable)
532 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
533 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
534 pcr->aspm_enabled = enable;
538 static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
540 if (pcr->aspm_enabled == enable)
543 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
545 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
547 pcr->aspm_enabled = enable;
550 static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable)
553 rts5261_enable_aspm(pcr, true);
555 rts5261_disable_aspm(pcr, false);
558 static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
560 struct rtsx_cr_option *option = &pcr->option;
564 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
565 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
577 rtsx_set_l1off_sub(pcr, val);
606 int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
621 if (is_version(pcr, PID_5261, IC_VER_D)) {
631 err = rtsx_pci_write_register(pcr, SD_CFG1,
637 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
642 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
643 clk, pcr->cur_clock);
645 if (clk == pcr->cur_clock)
648 if (pcr->ops->conv_clk_and_div_n)
649 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
661 if (pcr->ops->conv_clk_and_div_n) {
662 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
664 n = pcr->ops->conv_clk_and_div_n(dbl_clk,
673 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
699 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
701 rtsx_pci_init_cmd(pcr);
702 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
704 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
706 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
707 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
709 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
710 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
712 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
714 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
716 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
718 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
722 err = rtsx_pci_send_cmd(pcr, 2000);
728 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
732 pcr->cur_clock = clk;
737 void rts5261_init_params(struct rtsx_pcr *pcr)
739 struct rtsx_cr_option *option = &pcr->option;
740 struct rtsx_hw_param *hw_param = &pcr->hw_param;
742 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
743 pcr->num_slots = 1;
744 pcr->ops = &rts5261_pcr_ops;
746 pcr->flags = 0;
747 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
748 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
749 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
750 pcr->aspm_en = ASPM_L1_EN;
751 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
752 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
754 pcr->ic_version = rts5261_get_ic_version(pcr);
755 pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;
756 pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;
758 pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;