Lines Matching defs:pcr
16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
20 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
42 drive_sel = pcr->sd30_drive_sel_3v3;
45 drive_sel = pcr->sd30_drive_sel_1v8;
48 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
58 struct pci_dev *pdev = pcr->pci;
62 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
65 pcr_dbg(pcr, "skip fetch vendor setting\n");
69 pcr->aspm_en = rtsx_reg_to_aspm(reg);
70 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
71 pcr->card_drive_sel &= 0x3F;
72 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
75 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
77 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
78 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
80 pcr->flags |= PCR_REVERSE_SOCKET;
83 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
85 struct pci_dev *pdev = pcr->pci;
87 struct rtsx_cr_option *option = &(pcr->option);
96 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
98 rtsx_pci_enable_oobs_polling(pcr);
100 rtsx_pci_disable_oobs_polling(pcr);
105 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
108 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
111 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
114 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
123 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
130 static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
132 struct rtsx_cr_option *option = &(pcr->option);
134 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
143 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
151 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
155 pcr_dbg(pcr, "Enable efuse por!");
156 pcr_dbg(pcr, "save efuse to autoload");
158 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
159 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
163 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
167 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
173 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
175 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
179 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
183 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
184 rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
187 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
188 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
189 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
190 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
195 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
198 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
200 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
204 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
208 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
209 rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
211 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
212 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
214 pcr_dbg(pcr, "Disable efuse por!");
217 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
221 rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
223 rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
225 rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
228 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
231 pcr_dbg(pcr, "Power ON efuse!");
233 rts52xa_save_content_from_efuse(pcr);
235 rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
237 rts52xa_save_content_from_efuse(pcr);
240 pcr_dbg(pcr, "Load from autoload");
241 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
242 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
243 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
244 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
245 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
249 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
251 struct rtsx_cr_option *option = &(pcr->option);
253 rts5249_init_from_cfg(pcr);
254 rts5249_init_from_hw(pcr);
256 rtsx_pci_init_cmd(pcr);
258 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
259 rts52xa_save_content_to_autoload_space(pcr);
262 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
264 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
266 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
268 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
269 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
271 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
273 rts5249_fill_driving(pcr, OUTPUT_3V3);
274 if (pcr->flags & PCR_REVERSE_SOCKET)
275 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
277 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
279 rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
281 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
282 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
283 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
284 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
286 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
287 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
295 rtsx_pci_write_register(pcr, PETXCFG,
298 rtsx_pci_write_register(pcr, PETXCFG,
301 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
302 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
303 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
305 pcr_dbg(pcr, "Power OFF efuse!");
311 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
315 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
319 err = rtsx_pci_write_phy_register(pcr, PHY_REV,
330 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
336 err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
343 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
350 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
357 err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
361 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
365 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
371 return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
377 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
379 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
382 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
384 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
387 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
389 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
392 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
394 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
397 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
400 struct rtsx_cr_option *option = &pcr->option;
403 rtsx_pci_enable_ocp(pcr);
405 rtsx_pci_init_cmd(pcr);
406 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
408 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
410 err = rtsx_pci_send_cmd(pcr, 100);
416 rtsx_pci_init_cmd(pcr);
417 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
419 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
421 return rtsx_pci_send_cmd(pcr, 100);
424 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
426 struct rtsx_cr_option *option = &pcr->option;
429 rtsx_pci_disable_ocp(pcr);
431 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
433 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
437 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
444 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
451 if (CHK_PCI_PID(pcr, 0x5249)) {
452 err = rtsx_pci_update_phy(pcr, PHY_BACR,
459 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
465 pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
470 rtsx_pci_init_cmd(pcr);
471 rts5249_fill_driving(pcr, voltage);
472 return rtsx_pci_send_cmd(pcr, 100);
540 void rts5249_init_params(struct rtsx_pcr *pcr)
542 struct rtsx_cr_option *option = &(pcr->option);
544 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
545 pcr->num_slots = 2;
546 pcr->ops = &rts5249_pcr_ops;
548 pcr->flags = 0;
549 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
550 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
551 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
552 pcr->aspm_en = ASPM_L1_EN;
553 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
554 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
556 pcr->ic_version = rts5249_get_ic_version(pcr);
557 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
558 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
559 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
560 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
562 pcr->reg_pm_ctrl3 = PM_CTRL3;
578 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
582 return __rtsx_pci_write_phy_register(pcr, addr, val);
585 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
589 return __rtsx_pci_read_phy_register(pcr, addr, val);
592 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
596 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
601 rtsx_pci_write_phy_register(pcr, PHY_PCR,
604 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
607 if (is_version(pcr, 0x524A, IC_VER_A)) {
608 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
610 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
613 rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
616 rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
618 rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
628 rtsx_pci_write_phy_register(pcr, PHY_ANA08,
635 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
637 rts5249_extra_init_hw(pcr);
639 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
641 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
642 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
644 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
645 if (is_version(pcr, 0x524A, IC_VER_A)) {
646 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
648 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
650 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
652 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
654 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
656 rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
663 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
665 struct rtsx_cr_option *option = &(pcr->option);
667 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
672 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
673 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
686 if (rtsx_check_dev_flag(pcr,
694 rtsx_set_l1off_sub(pcr, val);
713 void rts524a_init_params(struct rtsx_pcr *pcr)
715 rts5249_init_params(pcr);
716 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
717 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
718 pcr->option.ltr_l1off_snooze_sspwrgate =
721 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
722 pcr->ops = &rts524a_pcr_ops;
724 pcr->option.ocp_en = 1;
725 if (pcr->option.ocp_en)
726 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
727 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
728 pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
732 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
734 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
736 return rtsx_base_card_power_on(pcr, card);
739 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
743 rtsx_pci_write_register(pcr, LDO_CONFIG2,
745 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
748 rtsx_pci_write_register(pcr, LDO_CONFIG2,
750 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
757 rtsx_pci_init_cmd(pcr);
758 rts5249_fill_driving(pcr, voltage);
759 return rtsx_pci_send_cmd(pcr, 100);
762 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
766 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
771 rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
776 rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
780 if (is_version(pcr, 0x525A, IC_VER_A))
781 rtsx_pci_write_phy_register(pcr, _PHY_REV0,
788 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
790 rts5249_extra_init_hw(pcr);
792 rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
794 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
795 if (is_version(pcr, 0x525A, IC_VER_A)) {
796 rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
798 rtsx_pci_write_register(pcr, RREF_CFG,
800 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
802 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
804 rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
806 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
808 rtsx_pci_write_register(pcr, OOBS_CONFIG,
829 void rts525a_init_params(struct rtsx_pcr *pcr)
831 rts5249_init_params(pcr);
832 pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
833 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
834 pcr->option.ltr_l1off_snooze_sspwrgate =
837 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
838 pcr->ops = &rts525a_pcr_ops;
840 pcr->option.ocp_en = 1;
841 if (pcr->option.ocp_en)
842 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
843 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
844 pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;