Lines Matching refs:WRITE_REG_CMD
57 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
59 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
61 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
63 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
64 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
66 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
68 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
127 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
130 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,