Lines Matching defs:pcr
19 static u8 rts5228_get_ic_version(struct rtsx_pcr *pcr)
23 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
27 static void rts5228_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
45 drive_sel = pcr->sd30_drive_sel_3v3;
48 drive_sel = pcr->sd30_drive_sel_1v8;
51 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
54 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
57 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
61 static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr)
63 struct pci_dev *pdev = pcr->pci;
68 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
71 pcr_dbg(pcr, "skip fetch vendor setting\n");
74 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
75 pcr->aspm_en = rtsx_reg_to_aspm(reg);
79 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
81 pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
83 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
84 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
86 pcr->flags |= PCR_REVERSE_SOCKET;
89 static int rts5228_optimize_phy(struct rtsx_pcr *pcr)
91 return rtsx_pci_write_phy_register(pcr, 0x07, 0x8F40);
94 static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
97 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
98 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
99 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
102 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
105 rtsx_pci_write_register(pcr, FPDCTL,
109 static int rts5228_enable_auto_blink(struct rtsx_pcr *pcr)
111 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
115 static int rts5228_disable_auto_blink(struct rtsx_pcr *pcr)
117 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
121 static int rts5228_turn_on_led(struct rtsx_pcr *pcr)
123 return rtsx_pci_write_register(pcr, GPIO_CTL,
127 static int rts5228_turn_off_led(struct rtsx_pcr *pcr)
129 return rtsx_pci_write_register(pcr, GPIO_CTL,
159 static int rts5228_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
161 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
163 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
164 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
166 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
171 static int rts5228_card_power_on(struct rtsx_pcr *pcr, int card)
173 struct rtsx_cr_option *option = &pcr->option;
176 rtsx_pci_enable_ocp(pcr);
178 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
181 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1,
184 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
187 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
191 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
196 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
199 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
202 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
204 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
205 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
209 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
210 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
214 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
215 pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
216 rts5228_sd_set_sample_push_timing_sd30(pcr);
221 static int rts5228_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
226 rtsx_pci_write_register(pcr, RTS5228_CARD_PWR_CTL,
231 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
233 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
237 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
239 rtsx_pci_write_register(pcr, SD_PAD_CTL,
243 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
245 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
249 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
251 rtsx_pci_write_register(pcr, SD_PAD_CTL,
259 rts5228_fill_driving(pcr, voltage);
264 static void rts5228_stop_cmd(struct rtsx_pcr *pcr)
266 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
267 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
268 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
271 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
274 static void rts5228_card_before_power_off(struct rtsx_pcr *pcr)
276 rts5228_stop_cmd(pcr);
277 rts5228_switch_output_voltage(pcr, OUTPUT_3V3);
280 static void rts5228_enable_ocp(struct rtsx_pcr *pcr)
285 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
286 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
291 static void rts5228_disable_ocp(struct rtsx_pcr *pcr)
296 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
297 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
301 static int rts5228_card_power_off(struct rtsx_pcr *pcr, int card)
305 rts5228_card_before_power_off(pcr);
306 err = rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
308 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, 0);
310 if (pcr->option.ocp_en)
311 rtsx_pci_disable_ocp(pcr);
316 static void rts5228_init_ocp(struct rtsx_pcr *pcr)
318 struct rtsx_cr_option *option = &pcr->option;
323 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
327 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
330 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
334 rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, &val);
337 val = pcr->hw_param.ocp_glitch;
338 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
340 rts5228_enable_ocp(pcr);
343 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
348 static void rts5228_clear_ocpstat(struct rtsx_pcr *pcr)
356 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
359 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
363 static void rts5228_process_ocp(struct rtsx_pcr *pcr)
365 if (!pcr->option.ocp_en)
368 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
370 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
371 rts5228_clear_ocpstat(pcr);
372 rts5228_card_power_off(pcr, RTSX_SD_CARD);
373 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
374 pcr->ocp_stat = 0;
379 static void rts5228_init_from_cfg(struct rtsx_pcr *pcr)
381 struct pci_dev *pdev = pcr->pci;
384 struct rtsx_cr_option *option = &pcr->option;
393 rtsx_pci_enable_oobs_polling(pcr);
395 rtsx_pci_disable_oobs_polling(pcr);
398 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
400 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
403 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
405 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
408 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
410 rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
413 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
415 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
417 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
421 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
425 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
431 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
438 static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
440 struct rtsx_cr_option *option = &pcr->option;
442 rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
445 rts5228_init_from_cfg(pcr);
447 rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
449 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
451 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
454 rtsx_pci_write_register(pcr, PCLK_CTL,
457 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
458 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
461 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
464 rts5228_fill_driving(pcr, OUTPUT_3V3);
466 if (pcr->flags & PCR_REVERSE_SOCKET)
467 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
469 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
476 rtsx_pci_write_register(pcr, PETXCFG,
479 rtsx_pci_write_register(pcr, PETXCFG,
482 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
483 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
484 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
490 static void rts5228_enable_aspm(struct rtsx_pcr *pcr, bool enable)
494 if (pcr->aspm_enabled == enable)
499 val |= (pcr->aspm_en & 0x02);
500 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
501 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
502 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
503 pcr->aspm_enabled = enable;
506 static void rts5228_disable_aspm(struct rtsx_pcr *pcr, bool enable)
510 if (pcr->aspm_enabled == enable)
513 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
517 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
518 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
520 pcr->aspm_enabled = enable;
523 static void rts5228_set_aspm(struct rtsx_pcr *pcr, bool enable)
526 rts5228_enable_aspm(pcr, true);
528 rts5228_disable_aspm(pcr, false);
531 static void rts5228_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
533 struct rtsx_cr_option *option = &pcr->option;
537 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
538 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
550 rtsx_set_l1off_sub(pcr, val);
581 int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
601 err = rtsx_pci_write_register(pcr, SD_CFG1,
607 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
612 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
613 clk, pcr->cur_clock);
615 if (clk == pcr->cur_clock)
618 if (pcr->ops->conv_clk_and_div_n)
619 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
631 if (pcr->ops->conv_clk_and_div_n) {
632 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
634 n = pcr->ops->conv_clk_and_div_n(dbl_clk,
643 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
669 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
671 rtsx_pci_init_cmd(pcr);
672 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
674 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
676 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
677 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
679 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
680 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
682 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
684 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
686 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
688 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
692 err = rtsx_pci_send_cmd(pcr, 2000);
698 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
702 pcr->cur_clock = clk;
707 void rts5228_init_params(struct rtsx_pcr *pcr)
709 struct rtsx_cr_option *option = &pcr->option;
710 struct rtsx_hw_param *hw_param = &pcr->hw_param;
712 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
713 pcr->num_slots = 1;
714 pcr->ops = &rts5228_pcr_ops;
716 pcr->flags = 0;
717 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
718 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
719 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
720 pcr->aspm_en = ASPM_L1_EN;
721 pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11);
722 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
724 pcr->ic_version = rts5228_get_ic_version(pcr);
725 pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl;
726 pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl;
728 pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3;