Lines Matching defs:pcr
17 static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
21 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
25 static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
43 drive_sel = pcr->sd30_drive_sel_3v3;
46 drive_sel = pcr->sd30_drive_sel_1v8;
49 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
51 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
53 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
57 static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
59 struct pci_dev *pdev = pcr->pci;
63 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
68 pcr->aspm_en = rtsx_reg_to_aspm(reg);
69 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
70 pcr->card_drive_sel &= 0x3F;
71 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
74 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
76 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
77 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
79 pcr->flags |= PCR_REVERSE_SOCKET;
82 static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
84 struct pci_dev *pdev = pcr->pci;
87 struct rtsx_cr_option *option = &pcr->option;
95 if (CHK_PCI_PID(pcr, 0x522A)) {
97 rtsx_pci_enable_oobs_polling(pcr);
99 rtsx_pci_disable_oobs_polling(pcr);
103 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
105 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
108 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
110 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
113 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
115 rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
118 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
120 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
125 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
129 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
135 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
143 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
146 struct rtsx_cr_option *option = &pcr->option;
148 rts5227_init_from_cfg(pcr);
149 rtsx_pci_init_cmd(pcr);
152 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
154 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
156 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
157 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
159 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
161 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
163 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
165 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
167 rts5227_fill_driving(pcr, OUTPUT_3V3);
169 if (pcr->flags & PCR_REVERSE_SOCKET)
170 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
172 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
175 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
178 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
181 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
183 return rtsx_pci_send_cmd(pcr, 100);
186 static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
190 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
195 return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
198 static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
200 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
203 static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
205 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
208 static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
210 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
213 static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
215 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
218 static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
222 if (pcr->option.ocp_en)
223 rtsx_pci_enable_ocp(pcr);
225 rtsx_pci_init_cmd(pcr);
226 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
229 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
232 err = rtsx_pci_send_cmd(pcr, 100);
238 rtsx_pci_init_cmd(pcr);
239 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
242 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
245 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
247 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
249 return rtsx_pci_send_cmd(pcr, 100);
252 static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
254 if (pcr->option.ocp_en)
255 rtsx_pci_disable_ocp(pcr);
257 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
259 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
264 static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
269 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
273 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
276 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
284 rtsx_pci_init_cmd(pcr);
285 rts5227_fill_driving(pcr, voltage);
286 return rtsx_pci_send_cmd(pcr, 100);
350 void rts5227_init_params(struct rtsx_pcr *pcr)
352 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
353 pcr->num_slots = 2;
354 pcr->ops = &rts5227_pcr_ops;
356 pcr->flags = 0;
357 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
358 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
359 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
360 pcr->aspm_en = ASPM_L1_EN;
361 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
362 pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
364 pcr->ic_version = rts5227_get_ic_version(pcr);
365 pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
366 pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
367 pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
368 pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
370 pcr->reg_pm_ctrl3 = PM_CTRL3;
373 static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
377 err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
382 if (is_version(pcr, 0x522A, IC_VER_A)) {
383 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
388 rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
389 rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
390 rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
391 rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
397 static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
399 rts5227_extra_init_hw(pcr);
402 if (!pcr->card_exist)
403 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
406 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
408 rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
409 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
410 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
415 static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
420 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
424 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
427 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
435 rtsx_pci_init_cmd(pcr);
436 rts5227_fill_driving(pcr, voltage);
437 return rtsx_pci_send_cmd(pcr, 100);
440 static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
442 struct rtsx_cr_option *option = &pcr->option;
446 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
447 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
459 rtsx_set_l1off_sub(pcr, val);
480 void rts522a_init_params(struct rtsx_pcr *pcr)
482 struct rtsx_cr_option *option = &pcr->option;
484 rts5227_init_params(pcr);
485 pcr->ops = &rts522a_pcr_ops;
486 pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
487 pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
500 pcr->option.ocp_en = 1;
501 if (pcr->option.ocp_en)
502 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
503 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
504 pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;