Lines Matching refs:val
561 u32 val;
565 val = readl(prcmu_base + reg);
566 val = ((val & ~mask) | (value & mask));
567 writel(val, (prcmu_base + reg));
592 * @val: Value to be set, i.e. transition requested
598 int prcmu_set_rc_a2p(enum romcode_write val)
600 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
602 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
643 u32 val;
671 val = readl(PRCM_CLKOCR);
672 if (val & div_mask) {
674 if ((val & mask) != bits) {
679 if ((val & mask & ~div_mask) != bits) {
685 writel((bits | (val & ~mask)), PRCM_CLKOCR);
871 u32 val;
874 val = readl(prcmu_base + clock_reg[i]);
875 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
888 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
890 writel(val, prcmu_base + clock_reg[i]);
1224 u32 val;
1232 val = 0;
1234 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1237 val |= PRCM_TCR_STOP_TIMERS |
1241 writel(val, PRCM_TCR);
1248 u32 val;
1257 val = readl(prcmu_base + clk_mgt[clock].offset);
1259 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1261 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1262 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1264 writel(val, prcmu_base + clk_mgt[clock].offset);
1276 u32 val;
1280 val = readl(PRCM_CGATING_BYPASS);
1281 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1287 val = readl(PRCM_CGATING_BYPASS);
1288 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1306 u32 val;
1312 val = readl(PRCM_PLLDSI_ENABLE);
1314 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1316 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1317 writel(val, PRCM_PLLDSI_ENABLE);
1334 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1335 writel(val, PRCM_PLLDSI_ENABLE);
1346 u32 val;
1348 val = readl(PRCM_DSI_PLLOUT_SEL);
1349 val &= ~dsiclk[n].divsel_mask;
1350 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1352 writel(val, PRCM_DSI_PLLOUT_SEL);
1358 u32 val;
1360 val = readl(PRCM_DSITVCLK_DIV);
1361 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1362 writel(val, PRCM_DSITVCLK_DIV);
1400 u32 val;
1404 val = readl(reg);
1407 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1409 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1413 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1417 if (val & PRCM_PLL_FREQ_SELDIV2)
1421 (val & PRCM_PLL_FREQ_DIV2EN) &&
1436 u32 val;
1440 val = readl(prcmu_base + clk_mgt[clock].offset);
1442 if (val & PRCM_CLK_MGT_CLK38) {
1443 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1448 val |= clk_mgt[clock].pllsw;
1449 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1461 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1467 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1468 if (val)
1469 return rate / val;
1596 u32 val;
1601 val = readl(prcmu_base + clk_mgt[clock].offset);
1602 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1605 if (val & PRCM_CLK_MGT_CLK38) {
1750 u32 val;
1761 val = readl(prcmu_base + clk_mgt[clock].offset);
1762 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1765 if (val & PRCM_CLK_MGT_CLK38) {
1768 val |= PRCM_CLK_MGT_CLK38DIV;
1770 val &= ~PRCM_CLK_MGT_CLK38DIV;
1773 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1780 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1784 val |= min(div, (u32)31);
1786 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1787 val |= min(div, (u32)31);
1789 writel(val, prcmu_base + clk_mgt[clock].offset);
1876 u32 val;
1886 val = readl(PRCM_DSI_PLLOUT_SEL);
1887 val &= ~dsiclk[n].divsel_mask;
1888 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1889 writel(val, PRCM_DSI_PLLOUT_SEL);
1894 u32 val;
1898 val = readl(PRCM_DSITVCLK_DIV);
1899 val &= ~dsiescclk[n].div_mask;
1900 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1901 writel(val, PRCM_DSITVCLK_DIV);
1985 static int config_hot_period(u16 val)
1992 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2203 u32 val;
2208 val = readl(PRCM_HOSTACCESS_REQ);
2209 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2219 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2220 writel(val, PRCM_HOSTACCESS_REQ);
2224 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2225 writel(val, PRCM_HOSTACCESS_REQ);
2244 u32 val;
2248 val = readl(PRCM_HOSTACCESS_REQ);
2249 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2252 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2698 u32 val;
2700 val = readl(PRCM_A9PL_FORCE_CLKEN);
2701 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2703 writel(val, (PRCM_A9PL_FORCE_CLKEN));