Lines Matching refs:tcdm_base
450 static __iomem void *tcdm_base;
586 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
602 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
615 return readb(tcdm_base + PRCM_ROMCODE_P2A);
625 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
705 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
706 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
707 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
709 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
710 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
720 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
747 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
748 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
749 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
791 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
792 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
794 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
818 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
819 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
820 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
841 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
925 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
926 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
928 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
956 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
990 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1020 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1050 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1051 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1104 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1105 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1107 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1167 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1168 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1199 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1201 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1930 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1932 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
1934 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
1935 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
1952 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
1953 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1970 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
1971 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
1973 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
1974 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1992 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
1993 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2026 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2027 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2028 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2029 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2031 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2109 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2110 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2111 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2112 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2113 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2159 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2160 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2161 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2162 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2163 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2282 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2294 return readw(tcdm_base + PRCM_SW_RST_REASON);
2307 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2328 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2347 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2351 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2352 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2354 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2380 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2381 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2383 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2385 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2394 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2411 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2439 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2440 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
3030 tcdm_base = devm_ioremap(&pdev->dev, res->start,
3032 if (!tcdm_base) {